skristiansson / wb_sdram_ctrlLinks
SDRAM controller with multiple wishbone slave ports
☆29Updated 6 years ago
Alternatives and similar repositories for wb_sdram_ctrl
Users that are interested in wb_sdram_ctrl are comparing it to the libraries listed below
Sorting:
- Wishbone interconnect utilities☆41Updated 3 months ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆27Updated 3 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 3 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 3 months ago
- IceCore Ice40 HX based modular core☆46Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- CologneChip GateMate FPGA Module: GMM-7550☆22Updated this week
- ☆17Updated 2 years ago
- Simplified environment for litex☆14Updated 4 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- A configurable USB 2.0 device core☆31Updated 4 years ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆30Updated 2 years ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆26Updated 9 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Miscellaneous ULX3S examples (advanced)☆77Updated last week
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆62Updated last week
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆98Updated last year
- Demo projects for various Kintex FPGA boards☆59Updated 2 weeks ago
- Fusesoc compatible rtl cores☆15Updated 2 years ago