GOOD-Stuff / FPGA-SPI-FlashLinks
Various projects of SPI loader module for xilinx fpga
☆31Updated 4 years ago
Alternatives and similar repositories for FPGA-SPI-Flash
Users that are interested in FPGA-SPI-Flash are comparing it to the libraries listed below
Sorting:
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆82Updated 5 years ago
- Video Stream Scaler☆40Updated 10 years ago
- EE 287 2012 Fall☆30Updated 12 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Python interface to PCIE☆39Updated 7 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆38Updated last year
- configurable cordic core in verilog☆51Updated 10 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.☆32Updated 6 years ago
- ☆15Updated 3 years ago
- FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic …☆15Updated 4 years ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆55Updated 4 years ago
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆48Updated 3 weeks ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 4 years ago
- ☆18Updated last year
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- ☆64Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Single Port RAM, Dual Port RAM, FIFO☆24Updated 3 years ago