caicaicai-ji / QSPI_FOR_SOCLinks
QSPI for SoC
☆22Updated 5 years ago
Alternatives and similar repositories for QSPI_FOR_SOC
Users that are interested in QSPI_FOR_SOC are comparing it to the libraries listed below
Sorting:
- SPI-Flash XIP Interface (Verilog)☆40Updated 3 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- ☆36Updated 9 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- A Voila-Jones face detector hardware implementation☆32Updated 6 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆63Updated last year
- Interface Protocol in Verilog☆50Updated 6 years ago
- Verilog SPI master and slave☆57Updated 9 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆59Updated 4 years ago
- ☆31Updated 5 years ago
- FPGA Technology Exchange Group相关文件管理☆45Updated 3 months ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆131Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆18Updated 5 years ago
- I2C controller core☆47Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆21Updated 5 years ago
- ☆73Updated 3 years ago
- UART -> AXI Bridge☆61Updated 4 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆19Updated last year
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- ☆16Updated 6 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆73Updated last year
- FPGA和USB3.0桥片实现USB3.0通信☆69Updated 3 years ago
- ☆29Updated 4 years ago