ZipCPU / sdspiLinks
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
☆299Updated 2 months ago
Alternatives and similar repositories for sdspi
Users that are interested in sdspi are comparing it to the libraries listed below
Sorting:
- Opensource DDR3 Controller☆362Updated last month
- A full-speed device-side USB peripheral core written in Verilog.☆232Updated 2 years ago
- A simple, basic, formally verified UART controller☆306Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆492Updated 3 years ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆273Updated last year
- WISHBONE SD Card Controller IP Core☆125Updated 2 years ago
- Verilog UART☆173Updated 12 years ago
- FPGA display controller with support for VGA, DVI, and HDMI.☆230Updated 5 years ago
- FPGA Logic Analyzer and GUI☆134Updated 2 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆250Updated 6 years ago
- High throughput JPEG decoder in Verilog for FPGA☆233Updated 3 years ago
- SPI Slave for FPGA in Verilog and VHDL☆203Updated last year
- Verilog implementation of a RISC-V core☆121Updated 6 years ago
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆280Updated 4 years ago
- SPI Master for FPGA - VHDL and Verilog☆296Updated last year
- Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…☆249Updated last month
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆271Updated 4 years ago
- USB3 PIPE interface for Xilinx 7-Series☆217Updated 3 years ago
- Small footprint and configurable DRAM core☆424Updated last week
- Verilog SDRAM memory controller☆335Updated 8 years ago
- iCESugar FPGA Board (base on iCE40UP5k)☆395Updated 2 months ago
- current focus on Colorlight i5 and i9 & i9plus module☆297Updated last month
- A simple implementation of a UART modem in Verilog.☆141Updated 3 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆173Updated last year
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆283Updated 3 weeks ago
- Bus bridges and other odds and ends☆572Updated 3 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆354Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆83Updated 2 years ago
- TangPrimer-20K-example project☆199Updated 8 months ago
- LiteX boards files☆420Updated last week