ZipCPU / sdspiLinks
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
☆286Updated last month
Alternatives and similar repositories for sdspi
Users that are interested in sdspi are comparing it to the libraries listed below
Sorting:
- Opensource DDR3 Controller☆333Updated last week
- A full-speed device-side USB peripheral core written in Verilog.☆231Updated 2 years ago
- FPGA Logic Analyzer and GUI☆131Updated 2 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆467Updated 3 years ago
- Verilog UART☆165Updated 11 years ago
- A simple, basic, formally verified UART controller☆303Updated last year
- USB3 PIPE interface for Xilinx 7-Series☆215Updated 3 years ago
- WISHBONE SD Card Controller IP Core☆122Updated 2 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆249Updated 6 years ago
- Bus bridges and other odds and ends☆560Updated last month
- SPI Slave for FPGA in Verilog and VHDL☆199Updated last year
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆169Updated last year
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆271Updated last year
- Small footprint and configurable DRAM core☆414Updated last week
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆349Updated last year
- FPGA display controller with support for VGA, DVI, and HDMI.☆228Updated 5 years ago
- Tang Mega 138K Pro examples☆70Updated last month
- Verilog implementation of a RISC-V core☆117Updated 6 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆269Updated 4 years ago
- Basic RISC-V Test SoC☆125Updated 6 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆236Updated this week
- A huge VHDL library for FPGA and digital ASIC development☆384Updated this week
- SPI Master for FPGA - VHDL and Verilog☆291Updated last year
- Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…☆245Updated last week
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆168Updated last week
- A simple implementation of a UART modem in Verilog.☆134Updated 3 years ago
- Basic USB-CDC device core (Verilog)☆78Updated 4 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆184Updated 5 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆136Updated 11 months ago
- High throughput JPEG decoder in Verilog for FPGA☆232Updated 3 years ago