A collection of debugging busses developed and presented at zipcpu.com
☆44Jan 18, 2024Updated 2 years ago
Alternatives and similar repositories for dbgbus
Users that are interested in dbgbus are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A wishbone controlled scope for FPGA's☆92Jan 12, 2024Updated 2 years ago
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago
- Wishbone SATA Controller☆28Jul 9, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A wishbone controlled PWM (audio) controller☆18Jan 16, 2024Updated 2 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- Wishbone interconnect utilities☆45Feb 23, 2026Updated 4 months ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- A utility for Composing FPGA designs from Peripherals☆191Jul 4, 2026Updated 2 weeks ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- FPGA纯逻辑实现modbus通信☆27Sep 5, 2022Updated 3 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated last year
- Bus bridges and other odds and ends☆688Jun 2, 2026Updated last month
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆17Oct 18, 2014Updated 11 years ago
- SPI Master Core clone from OpenCores☆14Oct 4, 2013Updated 12 years ago
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11Jun 26, 2026Updated 3 weeks ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 12 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- A wishbone controlled FM transmitter hack☆24Jan 16, 2024Updated 2 years ago
- A ZipCPU based demonstration of the MAX1000 FPGA board☆23May 11, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- A data acquisition framework in Python and Verilog.☆47Updated this week
- AHB3-Lite to Wishbone Bridge☆13Mar 26, 2019Updated 7 years ago
- Mega/Xmega soft core RTL design.☆11Feb 21, 2020Updated 6 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Apr 15, 2024Updated 2 years ago
- RISC-V Worlds provides isolation in a hardware platform by constraining access to system physical addresses.☆15Jun 25, 2026Updated 3 weeks ago
- vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.☆25Jan 7, 2016Updated 10 years ago
- A library to parse BLIF (Berkeley Logic Interchange Format) files.☆10Mar 11, 2015Updated 11 years ago
- Wishbone controlled I2C controllers☆57Updated this week
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Z-Core - A Lightweight RISC-V Processor (RV32IMZicsr)☆15Jun 26, 2026Updated 3 weeks ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 3 years ago
- Oasis is a lightweight modular framework allowing to easily write, build and patch instrumentation modules for Bluetooth Low Energy (BLE)…☆21Dec 5, 2023Updated 2 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 10 years ago
- FPGA based transmitter☆108Apr 14, 2017Updated 9 years ago