ZipCPU / fftdemoLinks
A demonstration showing how several components can be compsed to build a simulated spectrogram
☆45Updated last year
Alternatives and similar repositories for fftdemo
Users that are interested in fftdemo are comparing it to the libraries listed below
Sorting:
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated this week
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- assorted library of utility cores for amaranth HDL☆90Updated 8 months ago
- Collection of projects for various FPGA development boards☆44Updated last year
- Wishbone interconnect utilities☆41Updated 3 months ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆56Updated 4 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆43Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆113Updated 4 years ago
- ☆45Updated 2 years ago
- Projects published on controlpaths.com and hackster.io☆40Updated 2 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- Small footprint and configurable JESD204B core☆42Updated last week
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated last week
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated 3 months ago
- Project X-Ray Database: XC7 Series☆69Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year
- This repository contains synthesizable examples which use the PoC-Library.☆37Updated 4 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 months ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Updated 9 years ago
- USB Full Speed PHY☆44Updated 5 years ago