ZipCPU / fftdemoLinks
A demonstration showing how several components can be compsed to build a simulated spectrogram
☆46Updated last year
Alternatives and similar repositories for fftdemo
Users that are interested in fftdemo are comparing it to the libraries listed below
Sorting:
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated 3 weeks ago
- assorted library of utility cores for amaranth HDL☆95Updated 11 months ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆116Updated 4 years ago
- Nitro USB FPGA core☆87Updated last year
- A wishbone controlled scope for FPGA's☆83Updated last year
- VHDL library 4 FPGAs☆181Updated this week
- This repository contains small example designs that can be used with the open source icestorm flow.☆149Updated 3 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆175Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Wishbone controlled I2C controllers☆52Updated 9 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆64Updated last week
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- ☆135Updated 8 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 4 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆53Updated 2 months ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆59Updated 4 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆56Updated 2 years ago
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆77Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Verilog wishbone components☆117Updated last year
- Small footprint and configurable SPI core☆42Updated last month
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆109Updated 8 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Small footprint and configurable JESD204B core☆45Updated 3 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆98Updated 2 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆97Updated 5 years ago
- ☆45Updated 2 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆88Updated 2 years ago