ZipCPU / fftdemo
A demonstration showing how several components can be compsed to build a simulated spectrogram
☆40Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for fftdemo
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆60Updated 3 weeks ago
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- Wishbone controlled I2C controllers☆44Updated last week
- A padring generator for ASICs☆22Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆82Updated 6 years ago
- A wishbone controlled scope for FPGA's☆73Updated 10 months ago
- assorted library of utility cores for amaranth HDL☆81Updated 2 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- PicoRV☆43Updated 4 years ago
- Wishbone interconnect utilities☆37Updated 6 months ago
- Miscellaneous ULX3S examples (advanced)☆74Updated last year
- FPGA USB 1.1 Low-Speed Implementation☆33Updated 6 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆52Updated 3 years ago
- ☆40Updated 4 years ago
- Extensible FPGA control platform☆54Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Nitro USB FPGA core☆83Updated 8 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 10 months ago
- Small footprint and configurable JESD204B core☆40Updated last month
- Project X-Ray Database: XC7 Series☆63Updated 2 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆36Updated last year
- Using the TinyFPGA BX USB code in user designs☆49Updated 5 years ago
- Projects published on controlpaths.com and hackster.io☆40Updated 2 years ago
- Use ECP5 JTAG port to interact with user design☆24Updated 3 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆106Updated 3 years ago
- PMOD boards for ULX3S☆40Updated last year
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- Experiments with Yosys cxxrtl backend☆47Updated 11 months ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago