A demonstration showing how several components can be compsed to build a simulated spectrogram
☆47Apr 15, 2024Updated last year
Alternatives and similar repositories for fftdemo
Users that are interested in fftdemo are comparing it to the libraries listed below
Sorting:
- A configurable C++ generator of pipelined Verilog FFT cores☆255Apr 18, 2024Updated last year
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- A series of CORDIC related projects☆121Nov 12, 2024Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆42Jan 18, 2024Updated 2 years ago
- A wishbone controlled scope for FPGA's☆88Jan 12, 2024Updated 2 years ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- A super-powered version of devmem/devmem2 that uses a kernel module to reach all addresses☆11Dec 15, 2020Updated 5 years ago
- Wishbone SATA Controller☆24Oct 16, 2025Updated 4 months ago
- Ten channel, Sigma-Delta, low noise, 32-bit ADC breakboard☆13Mar 18, 2021Updated 4 years ago
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 6 years ago
- Proof-of-concept software for a low-cost correlated antenna array using inexpensive RTL-SDR dongles and single-board computers☆14Jun 29, 2017Updated 8 years ago
- ☆14Jan 31, 2020Updated 6 years ago
- Video digitizer add-on module for DE2-115 FPGA development board.☆13Apr 17, 2017Updated 8 years ago
- A basic Soft(Gate)ware Defined Radio architecture☆101Jan 18, 2024Updated 2 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- A wishbone controlled PWM (audio) controller☆18Jan 16, 2024Updated 2 years ago
- ☆10Dec 18, 2017Updated 8 years ago
- Projects using the Sipeed Tang Primer FPGA development board☆16Dec 6, 2020Updated 5 years ago
- LVGL + Micropython + Blockly☆19Jan 6, 2021Updated 5 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆62Jan 12, 2021Updated 5 years ago
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 6 years ago
- Audio Signal Processing SoC☆20Mar 13, 2018Updated 7 years ago
- verilog example to drive PCM5102 DAC with FPGA☆18Apr 30, 2018Updated 7 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆15Oct 3, 2023Updated 2 years ago
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- Verilog code for an efficient and scalable DFT calculator (using the FFT algorithm). Meant to be implemented on an Intel DE10-Lite FPGA d…☆19Jul 10, 2020Updated 5 years ago
- Code that goes with the Digilent Maker Space projects- to share and improve all code here is shared under the Creative Commons 3.0 Licens…☆20Jun 5, 2014Updated 11 years ago
- USB Full-Speed core written in migen/LiteX☆43Mar 14, 2019Updated 6 years ago
- A Video display simulator☆175May 16, 2025Updated 9 months ago
- Wishbone controlled I2C controllers☆57Nov 12, 2024Updated last year
- Bus bridges and other odds and ends☆639Apr 14, 2025Updated 10 months ago
- A wishbone controlled FM transmitter hack☆24Jan 16, 2024Updated 2 years ago
- Sample projects for esp-idf.☆18Dec 1, 2017Updated 8 years ago
- Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA☆207Feb 28, 2019Updated 7 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 7 years ago
- Stereo digital 2-way crossover filters processing I2S audio (16bit or 24bit) streams☆22May 13, 2024Updated last year
- A ZipCPU based demonstration of the MAX1000 FPGA board☆23May 11, 2021Updated 4 years ago
- FPGA USB stack written in LiteX☆132Jun 5, 2022Updated 3 years ago