Alternatives and similar repositories for Simple_UVM

Users that are interested in Simple_UVM are comparing it to the libraries listed below

• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆17Updated 4 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆12Updated 5 years ago
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆19Updated 6 years ago
• smartfoxdata / uvm_axi
  uvm_axi is a uvm package for modeling and verifying AXI protocol
  ☆18Updated 6 months ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆34Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆23Updated 5 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆20Updated 4 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆35Updated 5 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆18Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆25Updated 8 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆29Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆55Updated 8 years ago
• nelsoncsc / easyUVM
  A simple UVM example with DPI
  ☆41Updated 8 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆35Updated 3 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆23Updated 6 months ago
• kumarswamy12 / ROUTER-1-3
  verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL
  ☆13Updated 6 years ago
• rooinasuit / AXI_to_SPI
  Designing means to communicate as an SPI master, being a part of AXI interface
  ☆17Updated last year
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆68Updated 4 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆51Updated 3 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆34Updated 8 years ago
• taichi-ishitani / tvip-common
  ☆13Updated last year
• Vivek-Dave / UVM_TestBench_For_Single_Port_RAM
  A complete UVM TB for verification of single port 64KB RAM
  ☆15Updated 4 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆46Updated 5 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆25Updated 3 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆41Updated 5 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 11 years ago