Alternatives and similar repositories for Simple_UVM

Users that are interested in Simple_UVM are comparing it to the libraries listed below

• smartfoxdata / uvm_axi
  uvm_axi is a uvm package for modeling and verifying AXI protocol
  ☆20Updated 10 months ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆20Updated 5 years ago
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆19Updated 7 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆37Updated 5 years ago
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆19Updated 5 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 6 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆36Updated 3 years ago
• nelsoncsc / easyUVM
  A simple UVM example with DPI
  ☆45Updated 8 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆20Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆56Updated 8 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆30Updated 5 years ago
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆37Updated last year
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆72Updated 5 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆27Updated 3 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆37Updated 8 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆37Updated 4 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆31Updated 10 months ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆16Updated 5 years ago
• designsolver / ahb3_uvm_tb
  AMBA 3 AHB UVM TB
  ☆34Updated 6 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆17Updated 4 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 7 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• kumarswamy12 / ROUTER-1-3
  verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL
  ☆14Updated 6 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆20Updated 13 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆48Updated 5 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 10 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆24Updated 3 years ago