sergachev / spi_mem_programmer
Small (Q)SPI flash memory programmer in Verilog
☆59Updated 2 years ago
Alternatives and similar repositories for spi_mem_programmer:
Users that are interested in spi_mem_programmer are comparing it to the libraries listed below
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆75Updated 10 months ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆24Updated 6 years ago
- Verilog SPI master and slave☆50Updated 9 years ago
- Wishbone interconnect utilities☆38Updated last week
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆33Updated 10 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆65Updated 2 years ago
- USB 2.0 Device IP Core☆59Updated 7 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- An i2c master controller implemented in Verilog☆32Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- UART 16550 core☆33Updated 10 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆50Updated 4 years ago
- Verilog wishbone components☆113Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago
- Basic USB-CDC device core (Verilog)☆77Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆65Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- USB 1.1 Host and Function IP core☆20Updated 10 years ago
- I2C controller core☆38Updated 2 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆31Updated 3 years ago
- FPGA Logic Analyzer and GUI☆117Updated 2 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- Verilog digital signal processing components☆126Updated 2 years ago
- ☆15Updated 6 years ago