Alternatives and similar repositories for spi_mem_programmer:

Users that are interested in spi_mem_programmer are comparing it to the libraries listed below

• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆76Updated last year
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆37Updated 3 years ago
• freecores / uart16550
  UART 16550 core
  ☆34Updated 10 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated last year
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆73Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆53Updated 9 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆114Updated last year
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆65Updated 7 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆68Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆38Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆32Updated 3 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆53Updated 4 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆76Updated 3 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆79Updated 4 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆49Updated 10 years ago
• gtjennings1 / JPEG_Encoder
  ☆15Updated 6 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 3 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆89Updated 5 years ago
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆32Updated 4 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 4 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆42Updated 4 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• CospanDesign / nysa-sata
  ☆83Updated 7 years ago