Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU
☆17Oct 18, 2014Updated 11 years ago
Alternatives and similar repositories for implement-CRC-32-in-Verilog
Users that are interested in implement-CRC-32-in-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wishbone SATA Controller☆28Sep 17, 2026Updated last week
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 8 years ago
- The SoC Design for Time-Sensitive Networking (TSN)☆25Dec 5, 2025Updated 9 months ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆35Jul 1, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A collection of debugging busses developed and presented at zipcpu.com☆45Jan 18, 2024Updated 2 years ago
- FPGA纯逻辑实现modbus通信☆27Sep 5, 2022Updated 4 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 12 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 7 years ago
- Wishbone controlled I2C controllers☆63Aug 10, 2026Updated last month
- Wishbone interconnect utilities☆46Feb 23, 2026Updated 7 months ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆16Dec 29, 2016Updated 9 years ago
- Design and Simulation of 1K * 32 bit SRAM memory design.☆23Dec 15, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A Simple As Possible RISCV-32I core with debug module.☆42Dec 1, 2019Updated 6 years ago
- SPI Master Core clone from OpenCores☆14Oct 4, 2013Updated 12 years ago
- AHB3-Lite to Wishbone Bridge☆13Mar 26, 2019Updated 7 years ago
- A wishbone controlled PWM (audio) controller☆19Jan 16, 2024Updated 2 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Implementation of a circular queue in hardware using verilog.☆18Mar 22, 2019Updated 7 years ago
- Community evolution on Stack Overflow☆10Dec 10, 2018Updated 7 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 4 years ago
- ☆25Nov 4, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- FPGA Verilog HDL design project (DE1-SoC)☆13Jan 19, 2018Updated 8 years ago
- SRAM☆24Sep 6, 2020Updated 6 years ago
- Graphviz dot to Verilog Finite State Machine (FSM) generator written in Python☆15Feb 3, 2021Updated 5 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆20Sep 8, 2020Updated 6 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 10 months ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated 4 months ago
- ☆21Mar 5, 2023Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 中文文本相似度计算☆10Sep 1, 2018Updated 8 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 8 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- ☆13Jul 2, 2016Updated 10 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆164Feb 27, 2025Updated last year
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago