shalan / MS_QSPI_XIP_CACHELinks
AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
☆14Updated last year
Alternatives and similar repositories for MS_QSPI_XIP_CACHE
Users that are interested in MS_QSPI_XIP_CACHE are comparing it to the libraries listed below
Sorting:
- UART 16550 core☆37Updated 11 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- USB 1.1 Host and Function IP core☆23Updated 11 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 8 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆88Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆29Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- UART models for cocotb☆30Updated 2 weeks ago
- Wishbone interconnect utilities☆41Updated 7 months ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 7 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆95Updated 5 years ago
- Verilog I2C Slave☆23Updated 11 years ago
- USB Full Speed PHY☆46Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆29Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- turbo 8051☆29Updated 8 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 7 years ago