第四届全国大学生嵌入式比赛SoC
☆12Apr 1, 2022Updated 4 years ago
Alternatives and similar repositories for NPUSoC
Users that are interested in NPUSoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- 繁體中文等距更紗黑體+Nerd圖示字體庫。中英文寬度完美2:1,圖示長寬經過調整,不會出現對齊問題,尤其適合作為終端字體。☆34Dec 13, 2020Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- verilog/FPGA hardware description for very simple GPU☆16Apr 9, 2019Updated 7 years ago
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 9 years ago
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- Verilog-Based-NoC-Simulator☆11May 4, 2016Updated 10 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Voice Activity Detector based on MFCC features and DNN model☆29Jul 3, 2023Updated 2 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆172Mar 5, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- ☆14Aug 6, 2020Updated 5 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆44May 26, 2021Updated 4 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.☆13Mar 28, 2020Updated 6 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 13 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Direct Access Memory for MPSoC☆13May 3, 2026Updated 2 weeks ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆315Aug 16, 2018Updated 7 years ago
- ☆14Feb 24, 2025Updated last year
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- DMA core compatible with AHB3-Lite☆13Mar 30, 2019Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- A Full-System Framework for Simulating NDP devices from Caches to DRAM☆21Jan 12, 2024Updated 2 years ago
- ☆14Nov 11, 2015Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- ☆16Oct 30, 2021Updated 4 years ago
- tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog☆66Jul 14, 2021Updated 4 years ago
- A Visual RISC-V Simulator☆17Nov 7, 2023Updated 2 years ago
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆57May 10, 2021Updated 5 years ago