Alternatives and similar repositories for SD-card-controller:

Users that are interested in SD-card-controller are comparing it to the libraries listed below

• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆229Updated 2 years ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆257Updated 2 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆131Updated 2 years ago
• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆210Updated 2 years ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆244Updated 6 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆87Updated 10 months ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• projf / display_controller
  FPGA display controller with support for VGA, DVI, and HDMI.
  ☆225Updated 5 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆146Updated last month
• jamieiles / uart
  Verilog UART
  ☆148Updated 11 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆114Updated last year
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆308Updated last week
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆52Updated 9 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆69Updated 2 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆65Updated 7 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 4 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆126Updated 5 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆76Updated 13 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆89Updated 5 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆122Updated 4 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆80Updated 5 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆76Updated 3 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆76Updated 11 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆115Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆130Updated 2 months ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 2 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆67Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆119Updated 5 years ago