Alternatives and similar repositories for SD-card-controller

Users that are interested in SD-card-controller are comparing it to the libraries listed below

• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆97Updated 3 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆236Updated 3 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆62Updated 10 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆324Updated 2 years ago
• jamieiles / uart
  Verilog UART
  ☆192Updated 12 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆129Updated 6 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆69Updated last year
• ldoolitt / vhd2vl
  ☆140Updated this week
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆68Updated 3 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆135Updated 7 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆160Updated 11 months ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆266Updated 6 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆86Updated last year
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆125Updated 5 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆82Updated 3 years ago
• projf / display_controller
  FPGA display controller with support for VGA, DVI, and HDMI.
  ☆246Updated 2 weeks ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆100Updated 6 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆170Updated 6 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆70Updated 4 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆37Updated 11 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆285Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆74Updated 8 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆109Updated last year
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆84Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆153Updated 2 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆79Updated 3 years ago
• CospanDesign / nysa-sata
  ☆89Updated 8 years ago