manjushpv / Design-and-Verification-of-Nand-Flash-Memory-Controller
- Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash).
- Implemented operations : Controller Reset, Memory Erase, Program Page and Page Read.
- Functional Verification of DUT : Test Plan, Environment Setup, Constraint Randomization, Corner test cases covered.
- Programming Language : Syste…
☆17Updated 6 years ago
Related projects: ⓘ
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆17Updated 4 years ago
- ☆31Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆20Updated 4 years ago
- ☆16Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆34Updated 3 years ago
- ☆36Updated 7 years ago
- UART -> AXI Bridge☆52Updated 3 years ago
- Must-have verilog systemverilog modules☆23Updated 2 years ago
- ☆32Updated 9 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- ☆28Updated 4 years ago
- Verilog SPI master and slave☆45Updated 8 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆15Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 6 years ago
- 100 MB/s Ethernet MAC Layer Switch☆13Updated 10 years ago
- spi memory controller☆21Updated 7 years ago
- A 32 point radix-2 FFT module written in Verilog☆19Updated 4 years ago
- Implementation of the PCIe physical layer☆28Updated 4 years ago
- ☆14Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆27Updated 5 years ago
- The memory model was leveraged from micron.☆18Updated 6 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆40Updated 2 years ago
- ☆19Updated 4 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆34Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆55Updated last year
- ☆19Updated this week
- ☆43Updated 2 years ago
- AHB DMA 32 / 64 bits☆48Updated 10 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago