freecores / simple_spiLinks
SPI core
☆12Updated 10 years ago
Alternatives and similar repositories for simple_spi
Users that are interested in simple_spi are comparing it to the libraries listed below
Sorting:
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆35Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆82Updated 2 years ago
- I2C Slave☆13Updated 10 years ago
- UART 16550 core☆37Updated 10 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆14Updated 10 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆78Updated last year
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆13Updated 5 years ago
- PCI bridge☆18Updated 10 years ago
- I2C controller core☆43Updated 2 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- AHB DMA 32 / 64 bits☆55Updated 10 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆35Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- ☆36Updated 9 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆51Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆63Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- Generic AXI to APB bridge☆12Updated 10 years ago