freecores / simple_spi
SPI core
☆12Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for simple_spi
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆29Updated 3 years ago
- I2C Slave☆11Updated 10 years ago
- Small (Q)SPI flash memory programmer in Verilog☆55Updated 2 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆70Updated 7 months ago
- PCI bridge☆16Updated 10 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆62Updated last year
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 9 years ago
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- AHB3-Lite Interconnect☆81Updated 6 months ago
- Verilog SPI master and slave☆46Updated 8 years ago
- DDR2 memory controller written in Verilog☆72Updated 12 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- Wishbone interconnect utilities☆37Updated 5 months ago
- UART 16550 core☆30Updated 10 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- Minimal DVI / HDMI Framebuffer☆76Updated 4 years ago
- A Verilog implementation of a processor cache.☆19Updated 6 years ago
- UART -> AXI Bridge☆57Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆90Updated 3 years ago
- APB to I2C☆40Updated 10 years ago
- Generic AXI to AHB bridge☆15Updated 10 years ago
- SPI Slave for FPGA in Verilog and VHDL☆185Updated 6 months ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- I2C controller core☆33Updated last year
- Reed Solomon Decoder (204,188)☆11Updated 10 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 3 weeks ago