freecores / simple_spi
SPI core
☆12Updated 10 years ago
Alternatives and similar repositories for simple_spi:
Users that are interested in simple_spi are comparing it to the libraries listed below
- I2C Slave☆12Updated 10 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆32Updated 3 years ago
- UART 16550 core☆34Updated 10 years ago
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- PCI bridge☆18Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated 11 months ago
- An i2c master controller implemented in Verilog☆31Updated 7 years ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Verilog SPI master and slave☆52Updated 9 years ago
- APB to I2C☆39Updated 10 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 10 months ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- Verilog I2C Slave☆23Updated 10 years ago
- USB 2.0 Device IP Core☆65Updated 7 years ago
- SPI Master Core clone from OpenCores☆11Updated 11 years ago
- RISC-V compliant Timer IP☆13Updated 10 months ago
- AHB3-Lite Interconnect☆87Updated 10 months ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆13Updated 4 years ago
- UART -> AXI Bridge☆60Updated 3 years ago