Alternatives and similar repositories for dpll

Users that are interested in dpll are comparing it to the libraries listed below

• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆151Updated 4 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆61Updated 3 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆122Updated 2 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆110Updated 8 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 7 years ago
• filipamator / adpll
  All digital PLL
  ☆28Updated 7 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆62Updated this week
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆93Updated 4 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆57Updated 4 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆115Updated 4 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 4 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆118Updated last month
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆56Updated 2 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆154Updated last year
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆88Updated 2 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆57Updated 2 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆26Updated 2 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆72Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago