ZipCPU / dpllLinks
A collection of phase locked loop (PLL) related projects
☆106Updated last year
Alternatives and similar repositories for dpll
Users that are interested in dpll are comparing it to the libraries listed below
Sorting:
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆162Updated 3 years ago
- Control and Status Register map generator for HDL projects☆116Updated last week
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆59Updated 3 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆147Updated 3 months ago
- Verilog digital signal processing components☆139Updated 2 years ago
- A series of CORDIC related projects☆106Updated 6 months ago
- All digital PLL☆28Updated 7 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆87Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆60Updated this week
- Ethernet MAC 10/100 Mbps☆82Updated 5 years ago
- Verilog wishbone components☆115Updated last year
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- An open-source HDL register code generator fast enough to run in real time.☆68Updated this week
- Mathematical Functions in Verilog☆92Updated 4 years ago
- DPLL for phase-locking to 1PPS signal☆32Updated 8 years ago
- A collection of demonstration digital filters☆152Updated last year
- I2C controller core☆43Updated 2 years ago
- Verilog SPI master and slave☆54Updated 9 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- 10G Low Latency Ethernet☆54Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year