filipamator / adpllLinks
All digital PLL
☆28Updated 7 years ago
Alternatives and similar repositories for adpll
Users that are interested in adpll are comparing it to the libraries listed below
Sorting:
- A collection of phase locked loop (PLL) related projects☆111Updated last year
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Verilog digital signal processing components☆156Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆157Updated 7 months ago
- UART -> AXI Bridge☆63Updated 4 years ago
- Verilog RTL Design☆45Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆66Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆66Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- IEEE P1735 decryptor for VHDL☆36Updated 10 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆32Updated 4 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆31Updated 5 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆56Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 9 months ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- General Purpose AXI Direct Memory Access☆60Updated last year
- ☆79Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆52Updated 2 years ago
- Generate testbench for your verilog module.☆38Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆74Updated 2 years ago