All digital PLL
☆28Dec 19, 2017Updated 8 years ago
Alternatives and similar repositories for adpll
Users that are interested in adpll are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- All Digital Phase-Locked Loop☆13May 22, 2023Updated 3 years ago
- MATLAB Implementation of a Digital PLL☆17Aug 15, 2016Updated 9 years ago
- A collection of phase locked loop (PLL) related projects☆120Jan 18, 2024Updated 2 years ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆31Mar 4, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A digital phase-locked loop implemented on Spartan-6☆13Jul 10, 2018Updated 7 years ago
- FPGA version of CORDIC algorithm that evaluates all the trigonometric and anti-trigonometric functions.☆24Nov 20, 2019Updated 6 years ago
- ☆13Aug 25, 2022Updated 3 years ago
- Verilog implementation of a tapped delay line TDC☆48Sep 27, 2018Updated 7 years ago
- Decodes Compact Disc data from microscope images of a CD's surface☆12Jan 14, 2023Updated 3 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- "PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks" ACM ASIACCS 2…☆14Apr 13, 2026Updated last month
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆88Jun 12, 2023Updated 2 years ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆12Apr 14, 2026Updated last month
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆35May 28, 2021Updated 5 years ago
- ☆15Jun 30, 2025Updated 10 months ago
- OpenWrt for Arduino Yún☆13Jan 5, 2017Updated 9 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆16Apr 25, 2020Updated 6 years ago
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 9 years ago
- ☆22Jan 3, 2026Updated 4 months ago
- ☆13May 5, 2023Updated 3 years ago
- Implementation of tappped delay line TDC on FPGA☆14Dec 28, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24May 9, 2026Updated 2 weeks ago
- lz4 in python☆13Apr 20, 2017Updated 9 years ago
- 北京航空航天大学学位论文数据库，调整论文阅读清晰度，下载论文 PDF。☆13Dec 27, 2022Updated 3 years ago
- 2023年电赛B题国一 方案☆26Sep 8, 2023Updated 2 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 5 years ago
- RFIC design course developed at Johannes Kepler University, Department for Integrated Circuits☆40May 17, 2026Updated last week
- 包含常见的模拟调制解调及数字调制解调的 MATLAB 代码☆36Jul 18, 2023Updated 2 years ago
- ☆15Jul 25, 2017Updated 8 years ago
- ☆17May 26, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Time to Digital Converter on an FPGA☆17Oct 8, 2020Updated 5 years ago
- GIAnT, the Generic Implementation ANalysis Toolkit☆12Jul 4, 2018Updated 7 years ago
- 本项目集成了全网优秀的攻防工具项目，包含自动化利用，子域名、敏感目录、端口等扫描，各大中间件，cms漏洞利用工具以及应急响应等资料。☆13May 22, 2022Updated 4 years ago
- Simulink model for noise shaping SAR ADC☆13Mar 17, 2020Updated 6 years ago
- VSD workshop - Phase Locked Loop(PLL) IC Design☆17Aug 4, 2021Updated 4 years ago
- A Modular System for Flexible, High-Performance Traffic http://www.ict-mplane.eu/☆24Oct 4, 2018Updated 7 years ago
- Allows decoding of some 433MHz wireless temperature and humidity sensors☆21Mar 8, 2023Updated 3 years ago