Alternatives and similar repositories for adpll

Users that are interested in adpll are comparing it to the libraries listed below

• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆65Updated 10 months ago
• Starrynightzyq / Delta-Sigma-Modulator
  Delta-Sigma modulator (DSM) for fractional phase locked loop.
  ☆30Updated 4 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆44Updated last year
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 10 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆54Updated last year
• JoshuaEbenezer / FFT-cordic-HDL
  FFT implementation using CORDIC algorithm written in Verilog.
  ☆33Updated 6 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆64Updated 5 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆55Updated 4 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 5 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆40Updated 4 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆70Updated 4 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆59Updated last year
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆40Updated 3 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• manjushpv / Design-and-Verification-of-Nand-Flash-Memory-Controller
  - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash).
 - Implemented operations : …
  ☆21Updated 7 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆106Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆48Updated last year
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆63Updated 2 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆55Updated 3 years ago
• briansune / FFT-R22SDF
  R22SDF FFT VLSI/FPGA investigate and implementation
  ☆15Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆44Updated last year
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆59Updated 3 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆46Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆38Updated 3 years ago