filipamator / adpll
All digital PLL
☆24Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for adpll
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆54Updated 10 months ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- Xilinx AXI VIP example of use☆31Updated 3 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago
- Generate testbench for your verilog module.☆35Updated 6 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆47Updated last year
- UART -> AXI Bridge☆55Updated 3 years ago
- Verilog digital signal processing components☆104Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆57Updated 3 weeks ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆37Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆62Updated 3 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆142Updated 2 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆35Updated 11 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆42Updated 11 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- ☆33Updated 9 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.