All digital PLL
☆28Dec 19, 2017Updated 8 years ago
Alternatives and similar repositories for adpll
Users that are interested in adpll are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- All Digital Phase-Locked Loop☆13May 22, 2023Updated 2 years ago
- MATLAB Implementation of a Digital PLL☆17Aug 15, 2016Updated 9 years ago
- All-Digital Phase-Locked Loops (ADPLL) code in High Speed Integrated Circuit Hardware Description Language (VHDL) for a Field Programmabl…☆12Oct 20, 2025Updated 5 months ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆14Feb 17, 2023Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆118Jan 18, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- A digital phase-locked loop implemented on Spartan-6☆13Jul 10, 2018Updated 7 years ago
- ☆13Aug 25, 2022Updated 3 years ago
- Verilog implementation of a tapped delay line TDC☆48Sep 27, 2018Updated 7 years ago
- Decodes Compact Disc data from microscope images of a CD's surface☆12Jan 14, 2023Updated 3 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆82Jun 12, 2023Updated 2 years ago
- "PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks" ACM ASIACCS 2…☆14Feb 11, 2026Updated last month
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆70Feb 1, 2015Updated 11 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆12Jul 3, 2025Updated 8 months ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- ☆11May 7, 2018Updated 7 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆34May 28, 2021Updated 4 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆271Mar 26, 2022Updated 4 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- OpenWrt for Arduino Yún☆13Jan 5, 2017Updated 9 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆15Apr 25, 2020Updated 5 years ago
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 9 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆21Jan 3, 2026Updated 2 months ago
- ☆13May 5, 2023Updated 2 years ago
- Implementation of tappped delay line TDC on FPGA☆14Dec 28, 2022Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Updated this week
- This repository consists of the processing of the recieved GPS signals at the receiver side. MATLAB has been put to use. MATLAB to HDL ma…☆19Jul 12, 2017Updated 8 years ago
- RFIC design course developed at Johannes Kepler University, Department for Integrated Circuits☆37Updated this week
- 2023年电 赛B题国一方案☆25Sep 8, 2023Updated 2 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆17Aug 31, 2020Updated 5 years ago
- 包含常见的模拟调制解调及数字调制解调的 MATLAB 代码☆34Jul 18, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆17May 26, 2021Updated 4 years ago
- GIAnT, the Generic Implementation ANalysis Toolkit☆12Jul 4, 2018Updated 7 years ago
- MATLAB 2019a functions for easy, data acquisition from the Siglent SDS1202X-E oscilloscope via USB or Ethernet. It also works with other …☆15Apr 19, 2020Updated 5 years ago
- VSD workshop - Phase Locked Loop(PLL) IC Design☆15Aug 4, 2021Updated 4 years ago
- Simulink model for noise shaping SAR ADC☆12Mar 17, 2020Updated 6 years ago
- A Modular System for Flexible, High-Performance Traffic http://www.ict-mplane.eu/☆24Oct 4, 2018Updated 7 years ago
- Allows decoding of some 433MHz wireless temperature and humidity sensors☆21Mar 8, 2023Updated 3 years ago