All digital PLL
☆29Dec 19, 2017Updated 8 years ago
Alternatives and similar repositories for adpll
Users that are interested in adpll are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- All Digital Phase-Locked Loop☆14May 22, 2023Updated 3 years ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆15Feb 17, 2023Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆122Jan 18, 2024Updated 2 years ago
- A digital phase-locked loop implemented on Spartan-6☆14Jul 10, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆32Mar 4, 2023Updated 3 years ago
- FPGA version of CORDIC algorithm that evaluates all the trigonometric and anti-trigonometric functions.☆25Nov 20, 2019Updated 6 years ago
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆75Feb 1, 2015Updated 11 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆95Jun 12, 2023Updated 3 years ago
- "PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks" ACM ASIACCS 2…☆14Jul 21, 2026Updated 3 weeks ago
- ☆13Aug 25, 2022Updated 3 years ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 9 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- OpenWrt for Arduino Yún☆13Jan 5, 2017Updated 9 years ago
- Implementation of tappped delay line TDC on FPGA☆16Dec 28, 2022Updated 3 years ago
- All-Digital Phase-Locked Loops (ADPLL) code in High Speed Integrated Circuit Hardware Description Language (VHDL) for a Field Programmabl…☆13Oct 20, 2025Updated 9 months ago
- ☆22Jan 3, 2026Updated 7 months ago
- 2023年电赛B题国一方案☆27Sep 8, 2023Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Jul 16, 2026Updated last month
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 5 years ago
- lz4 in python☆13Apr 20, 2017Updated 9 years ago
- VSD workshop - Phase Locked Loop(PLL) IC Design☆17Aug 4, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Basic Simulink Blocks for modeling CDRs and PLLs☆17Apr 25, 2020Updated 6 years ago
- ☆17May 26, 2021Updated 5 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆36May 28, 2021Updated 5 years ago
- ☆13May 5, 2023Updated 3 years ago
- ☆15Jul 25, 2017Updated 9 years ago
- 包含常见的模拟调制解调及数字调制解调的 MATLAB 代码☆37Jul 18, 2023Updated 3 years ago
- Time to Digital Converter on an FPGA☆18Oct 8, 2020Updated 5 years ago
- MATLAB 2019a functions for easy, data acquisition from the Siglent SDS1202X-E oscilloscope via USB or Ethernet. It also works with other …☆16Apr 19, 2020Updated 6 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- GIAnT, the Generic Implementation ANalysis Toolkit☆12Jul 4, 2018Updated 8 years ago
- This is a complementary extension to the https://hub.docker.com/r/hpretl/iic-osic-tools Docker image, adding support for RF simulations a…☆17Apr 6, 2026Updated 4 months ago
- 本项目集成了全网优秀的攻防工具项目,包含自动化利用,子域名、敏感目录、端口等扫描,各大中间件,cms漏洞利用工具以及应急响应等资料。☆13May 22, 2022Updated 4 years ago
- Building your own SDR DDC/DUC transceiver with DIY modules from aliexpress☆33Nov 11, 2019Updated 6 years ago
- Simulink model for noise shaping SAR ADC☆13Mar 17, 2020Updated 6 years ago
- 配套代码《FPGA Verilog开发实战指南——基于Altera EP4CE10》☆15Jul 22, 2021Updated 5 years ago
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆16Apr 14, 2026Updated 4 months ago