filipamator / adpll
All digital PLL
☆24Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for adpll
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆37Updated 11 months ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆56Updated 10 months ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆143Updated 2 years ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- SDRAM controller with AXI4 interface☆78Updated 5 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆24Updated 3 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆44Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆46Updated 7 months ago
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆55Updated 9 months ago
- UART -> AXI Bridge☆58Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆55Updated 3 months ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆41Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆43Updated 11 months ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆47Updated last year
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…☆13Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆84Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- AXI Interconnect☆46Updated 3 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- Verilog digital signal processing components☆108Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆99Updated 10 months ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆26Updated 3 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆41Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆27Updated 2 years ago