All digital PLL
☆31Dec 19, 2017Updated 8 years ago
Alternatives and similar repositories for adpll
Users that are interested in adpll are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- All Digital Phase-Locked Loop☆15May 22, 2023Updated 3 years ago
- MATLAB Implementation of a Digital PLL☆17Aug 15, 2016Updated 10 years ago
- MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/☆10Feb 4, 2022Updated 4 years ago
- A collection of phase locked loop (PLL) related projects☆123Jan 18, 2024Updated 2 years ago
- Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Veril…☆32Mar 4, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Project: Precise Measure of time delays in FPGA☆33Aug 3, 2017Updated 9 years ago
- Verilog implementation of a tapped delay line TDC☆51Sep 27, 2018Updated 8 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆98Jun 12, 2023Updated 3 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆17Aug 24, 2024Updated 2 years ago
- ☆13Aug 25, 2022Updated 4 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆304Mar 26, 2022Updated 4 years ago
- ☆11May 7, 2018Updated 8 years ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- "PLI-TDC: Super Fine Delay-Time Based Physical-Layer Identification with Time-to-Digital Converter for In-Vehicle Networks" ACM ASIACCS 2…☆15Aug 27, 2026Updated last month
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆14Nov 25, 2014Updated 11 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- OpenWrt for Arduino Yún☆13Jan 5, 2017Updated 9 years ago
- Implementation of tappped delay line TDC on FPGA☆16Dec 28, 2022Updated 3 years ago
- 2023年电赛B题国一方案☆28Sep 8, 2023Updated 3 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Updated this week
- PAST SHORT COURSES AND TUTORIALS FROM ISSCC.☆19Apr 7, 2024Updated 2 years ago
- lz4 in python☆13Apr 20, 2017Updated 9 years ago
- VSD workshop - Phase Locked Loop(PLL) IC Design☆18Aug 4, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 6 years ago
- 北京航空航天大学学位论文数据库，调整论文阅读清晰度，下载论文 PDF。☆13Dec 27, 2022Updated 3 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆17Apr 25, 2020Updated 6 years ago
- ☆17May 26, 2021Updated 5 years ago
- ☆13May 5, 2023Updated 3 years ago
- ☆15Jul 25, 2017Updated 9 years ago
- 包含常见的模拟调制解调及数字调制解调的 MATLAB 代码☆37Jul 18, 2023Updated 3 years ago
- MATLAB 2019a functions for easy, data acquisition from the Siglent SDS1202X-E oscilloscope via USB or Ethernet. It also works with other …☆16Apr 19, 2020Updated 6 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Time to Digital Converter on an FPGA☆18Oct 8, 2020Updated 6 years ago
- My blog☆11Jul 6, 2025Updated last year
- GIAnT, the Generic Implementation ANalysis Toolkit☆12Jul 4, 2018Updated 8 years ago
- This is a complementary extension to the https://hub.docker.com/r/hpretl/iic-osic-tools Docker image, adding support for RF simulations a…☆17Aug 18, 2026Updated last month
- 本项目集成了全网优秀的攻防工具项目，包含自动化利用，子域名、敏感目录、端口等扫描，各大中间件，cms漏洞利用工具以及应急响应等资料。☆13May 22, 2022Updated 4 years ago
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 8 years ago
- Simulink model for noise shaping SAR ADC☆14Mar 17, 2020Updated 6 years ago