Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
☆32Jun 8, 2017Updated 9 years ago
Alternatives and similar repositories for OpenRIO
Users that are interested in OpenRIO are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wishbone <-> AXI converters☆13Jun 1, 2015Updated 11 years ago
- Yilong's NetFPGA-10G Repo☆13May 7, 2015Updated 11 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆31Dec 1, 2016Updated 9 years ago
- Xilinx Virtual Cable Daemon☆20Nov 20, 2019Updated 6 years ago
- Synchronous Slave FIFO Interface between Xilinx Spartan 3E and Cypress FX3☆15Mar 11, 2015Updated 11 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆20Nov 10, 2017Updated 8 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆45May 12, 2016Updated 10 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13May 5, 2015Updated 11 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- ☆94May 4, 2017Updated 9 years ago
- high level VHDL floating point library for synthesis in fpga☆18Sep 4, 2026Updated 2 weeks ago
- VHDL Library for implementing common DSP functionality.☆33Oct 5, 2018Updated 7 years ago
- Igloo2 M2GL025 Creative Development Board☆11Oct 15, 2019Updated 6 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Apr 17, 2016Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Sata 2 Host Controller for FPGA implementation☆18Oct 11, 2017Updated 8 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 8 years ago
- ☆42Dec 11, 2025Updated 9 months ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆104Jun 6, 2020Updated 6 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆19Oct 23, 2019Updated 6 years ago
- Wishbone to AXI bridge (VHDL)☆51Aug 29, 2019Updated 7 years ago
- A revised version of Avery Pennarun's redo.☆10Nov 9, 2022Updated 3 years ago
- High-througput logic analyzer for FPGA☆17Oct 8, 2020Updated 5 years ago
- UDP/IP Core☆12Jul 17, 2014Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆24Apr 27, 2023Updated 3 years ago
- JESD204 Eye Scan Visualization Utility☆19Sep 14, 2026Updated last week
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 6 months ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 5 years ago
- ☆20Aug 2, 2025Updated last year
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Project in course “FPGA Design for Communication Systems”☆16Dec 30, 2023Updated 2 years ago
- Verilog wishbone components☆135Jan 5, 2024Updated 2 years ago
- TI HEX-BUS SD Drive Interface☆17Jun 12, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- JESD204b modules in VHDL☆31Apr 18, 2019Updated 7 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- 控制组生存指南☆10Jun 28, 2019Updated 7 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆16Jun 15, 2016Updated 10 years ago
- MessagePack implementation for VHDL☆11Nov 29, 2017Updated 8 years ago
- This project aims to implement a digital predistortion algorithm for power amplifier linearizion using vhdl. It contains VHDL design for …☆18Jan 11, 2023Updated 3 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 6 years ago