intel / multi_power_sequencer
Multi-Rail Power Sequencer, capable of monitoring and sequencing up to 144 power rails, offers a configurable and rich set of features, such as dynamic adjustments and debug via PMBus, adjustable timing, power rail grouping, etc.
☆17Updated 2 months ago
Alternatives and similar repositories for multi_power_sequencer:
Users that are interested in multi_power_sequencer are comparing it to the libraries listed below
- Small footprint and configurable JESD204B core☆41Updated last month
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- Extensible FPGA control platform☆57Updated last year
- ☆30Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Small footprint and configurable SPI core☆41Updated last month
- This repository contains synthesizable examples which use the PoC-Library.☆36Updated 4 years ago
- ☆20Updated 2 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆34Updated 7 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆54Updated this week
- Fork of OpenCores jpegencode with Cocotb testbench☆43Updated 9 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 4 years ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- An abstract language model of VHDL written in Python.☆50Updated this week
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆67Updated 7 years ago
- ☆16Updated 4 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆43Updated 3 years ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆22Updated 3 years ago
- assorted library of utility cores for amaranth HDL☆86Updated 5 months ago
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆76Updated 2 months ago
- general-cores☆18Updated 5 months ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆20Updated this week
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated this week