intel / multi_power_sequencer
Multi-Rail Power Sequencer, capable of monitoring and sequencing up to 144 power rails, offers a configurable and rich set of features, such as dynamic adjustments and debug via PMBus, adjustable timing, power rail grouping, etc.
☆18Updated 2 weeks ago
Alternatives and similar repositories for multi_power_sequencer
Users that are interested in multi_power_sequencer are comparing it to the libraries listed below
Sorting:
- Extensible FPGA control platform☆60Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆43Updated 3 years ago
- Small footprint and configurable JESD204B core☆42Updated 3 weeks ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- ☆30Updated 4 years ago
- Connecting FPGA and MCU using Ethernet RMII☆23Updated 9 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- An abstract language model of VHDL written in Python.☆52Updated last week
- VHDL PCIe Transceiver☆28Updated 4 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆20Updated 9 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago
- Eclipse based IDE for RISC-V bare metal software development.☆18Updated 5 years ago
- Vivado build system☆68Updated 4 months ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- ☆26Updated last year
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆57Updated this week
- This repository contains synthesizable examples which use the PoC-Library.☆37Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆6Updated 2 weeks ago
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 3 years ago
- ☆17Updated 4 years ago
- Triple Modular Redundancy☆26Updated 5 years ago
- ☆32Updated 2 years ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago