intel / multi_power_sequencerLinks
Multi-Rail Power Sequencer, capable of monitoring and sequencing up to 144 power rails, offers a configurable and rich set of features, such as dynamic adjustments and debug via PMBus, adjustable timing, power rail grouping, etc.
☆19Updated 8 months ago
Alternatives and similar repositories for multi_power_sequencer
Users that are interested in multi_power_sequencer are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable JESD204B core☆50Updated 2 months ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆45Updated 4 years ago
- Dockerized FPGA toolchain experiments☆29Updated last year
- ☆113Updated 9 months ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆106Updated this week
- A testbench for an axi lite custom IP☆23Updated 11 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆39Updated 5 years ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆72Updated 8 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 10 months ago
- An abstract language model of VHDL written in Python.☆59Updated last month
- Serial communication link bit error rate tester simulator, written in Python.☆120Updated 2 weeks ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Triple Modular Redundancy☆28Updated 6 years ago
- general-cores☆21Updated 5 months ago
- SDK for FPGA / Linux Instruments☆107Updated 2 months ago
- Vivado build system☆70Updated last month
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆43Updated last month
- ☆89Updated 8 years ago
- VHDL PCIe Transceiver☆32Updated 5 years ago
- ☆26Updated 2 years ago
- migen + misoc + redpitaya = digital servo☆41Updated 6 years ago
- ☆30Updated 4 years ago
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆12Updated 2 weeks ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Updated 10 months ago