intel / multi_power_sequencerLinks
Multi-Rail Power Sequencer, capable of monitoring and sequencing up to 144 power rails, offers a configurable and rich set of features, such as dynamic adjustments and debug via PMBus, adjustable timing, power rail grouping, etc.
☆19Updated 6 months ago
Alternatives and similar repositories for multi_power_sequencer
Users that are interested in multi_power_sequencer are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable JESD204B core☆49Updated last month
- Extensible FPGA control platform☆61Updated 2 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆45Updated 3 years ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆70Updated 8 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated last week
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆39Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- Vivado build system☆69Updated 2 weeks ago
- ☆87Updated 8 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- ☆112Updated 8 months ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- Python script to transform a VCD file to wavedrom format☆81Updated 3 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆83Updated 5 years ago
- A wishbone controlled scope for FPGA's☆84Updated last year
- ☆26Updated 2 years ago
- Xilinx virtual cable server for generic FTDI 4232H.☆59Updated last year
- VHDL-2008 Support Library☆57Updated 9 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- Eclipse based IDE for RISC-V bare metal software development.☆20Updated 6 years ago
- Wishbone to AXI bridge (VHDL)☆43Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆68Updated 2 months ago
- A testbench for an axi lite custom IP☆23Updated 10 years ago
- assorted library of utility cores for amaranth HDL☆97Updated last year
- Verilog wishbone components☆123Updated last year
- Triple Modular Redundancy☆27Updated 6 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago