intel / multi_power_sequencer
Multi-Rail Power Sequencer, capable of monitoring and sequencing up to 144 power rails, offers a configurable and rich set of features, such as dynamic adjustments and debug via PMBus, adjustable timing, power rail grouping, etc.
☆18Updated 4 months ago
Alternatives and similar repositories for multi_power_sequencer:
Users that are interested in multi_power_sequencer are comparing it to the libraries listed below
- Small footprint and configurable JESD204B core☆42Updated 3 months ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- VHDL PCIe Transceiver☆28Updated 4 years ago
- Vivado build system☆68Updated 4 months ago
- tinyVision.ai Vision & Sensor FPGA System on Module☆46Updated 3 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆43Updated 3 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆55Updated this week
- This repository contains synthesizable examples which use the PoC-Library.☆37Updated 4 years ago
- Extensible FPGA control platform☆59Updated last year
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- ☆30Updated 4 years ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 4 years ago
- Triple Modular Redundancy☆26Updated 5 years ago
- ☆33Updated last year
- general-cores☆18Updated 7 months ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago
- JESD204b modules in VHDL☆29Updated 6 years ago
- An open-source VHDL library for FPGA design.☆31Updated 2 years ago
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 3 weeks ago
- Small footprint and configurable SPI core☆41Updated this week
- Revision Control Labs and Materials☆24Updated 7 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆20Updated 9 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆88Updated last month
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- UART To SPI☆17Updated 10 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago