Alternatives and similar repositories for multi_power_sequencer

Users that are interested in multi_power_sequencer are comparing it to the libraries listed below

• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆50Updated 3 weeks ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆35Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• Avnet / hdl
  ☆114Updated 10 months ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆115Updated this week
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆45Updated 4 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• quartiq / redpid
  migen + misoc + redpitaya = digital servo
  ☆41Updated 7 years ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• alexforencich / fpga-utils
  Various utilities for working with FPGAs
  ☆13Updated 9 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆65Updated 2 months ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆72Updated 8 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆70Updated last month
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• VHDL / awesome-vhdl
  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
  ☆83Updated 5 years ago
• CospanDesign / nysa-sata
  ☆89Updated 8 years ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆90Updated 11 months ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆44Updated 6 years ago
• frobino / axi_custom_ip_tb
  A testbench for an axi lite custom IP
  ☆23Updated 11 years ago
• Gekkio / docker-fpga
  Dockerized FPGA toolchain experiments
  ☆29Updated last year
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 5 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆81Updated this week
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆32Updated 5 years ago
• capn-freako / PyBERT
  Serial communication link bit error rate tester simulator, written in Python.
  ☆120Updated this week
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 11 months ago