8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
☆18Jul 21, 2022Updated 4 years ago
Alternatives and similar repositories for vsd_pll
Users that are interested in vsd_pll are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VSD workshop - Phase Locked Loop(PLL) IC Design☆18Aug 4, 2021Updated 5 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Feb 16, 2022Updated 4 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- ☆12Jan 21, 2021Updated 5 years ago
- Open Analog Design Environment☆27May 19, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆35Feb 21, 2019Updated 7 years ago
- SRAM☆24Sep 6, 2020Updated 6 years ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 5 years ago
- ☆16Apr 8, 2023Updated 3 years ago
- ☆14Apr 13, 2025Updated last year
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆14Feb 2, 2022Updated 4 years ago
- A Vivado IP package of the PicoRV32 RISC-V processor☆16Jul 9, 2020Updated 6 years ago
- Open stadard cell library for open 28nm process☆18Jul 5, 2023Updated 3 years ago
- Zero to ASIC group submission for MPW2☆13Mar 26, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Verilog ADC interface for adc128s022 found in De0 Nano☆16Jul 7, 2015Updated 11 years ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 4 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆16Jul 6, 2025Updated last year
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 5 years ago
- Scripts for evaluation of SOTA SLAM algorithms included the necessary data loaders for the main SLAM datasets☆19Feb 5, 2024Updated 2 years ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- FPGA (Verilog) implementation of the Flip01 8-bit processor.☆18Dec 30, 2024Updated last year
- This repository contains source code that is aimed at converting a Spice NetList to its corresponding layout.☆28Mar 29, 2021Updated 5 years ago
- Implements NCurses Disk Usage(ncdu) with golang☆45Jul 10, 2023Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A series of simulations organized as homework assignments that were part of the course on Neuromorphic Engineering at IIT Bombay (course …☆10Jul 19, 2016Updated 10 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆25Jan 20, 2021Updated 5 years ago
- The source code of "Agents of Autonomy: A Systematic Study of Robotics on Modern Hardware" paper☆32Dec 18, 2023Updated 2 years ago
- EC499: Major Project☆11Jun 25, 2023Updated 3 years ago
- In this project, the simulation of simple digital hearing aid was developed using MATLAB programming language. The implementation of this…☆10Nov 11, 2021Updated 4 years ago
- Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction☆12Apr 21, 2022Updated 4 years ago
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆20Apr 10, 2023Updated 3 years ago
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆21Dec 15, 2020Updated 5 years ago
- A collection of phase locked loop (PLL) related projects☆123Jan 18, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This repository describes two frameworks which can be used for pre-Silicon power side-channel analysis of digital circuit designs (i.e., …☆16Feb 16, 2022Updated 4 years ago
- Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.☆17Apr 13, 2023Updated 3 years ago
- 32-bit RISC-V based processor with memory controler☆16Sep 2, 2022Updated 4 years ago
- IEEE Executive project for the year 2021-2022☆15Nov 22, 2022Updated 3 years ago
- Implementation of an Artificial Neural Network (ANN) on FPGA using VHDL☆13Jun 22, 2016Updated 10 years ago
- Many peripherals in Verilog ready to use☆41Dec 29, 2024Updated last year
- Recursive unified ORAM☆15Sep 23, 2015Updated 11 years ago