Alternatives and similar repositories for dblclockfft

Users that are interested in dblclockfft are comparing it to the libraries listed below

• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆113Updated 4 years ago
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆152Updated last year
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆168Updated last week
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆139Updated 2 years ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last week
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆87Updated 2 years ago
• benreynwar / fft-dit-fpga
  Verilog module for calculation of FFT.
  ☆174Updated 12 years ago
• mattvenn / fpga-sdft
  sliding DFT for FPGA, targetting Lattice ICE40 1k
  ☆77Updated 5 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆106Updated 6 months ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆147Updated 3 months ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆236Updated this week
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆89Updated 6 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆231Updated 2 years ago
• kevinpt / vhdl-extras
  Flexible VHDL library
  ☆185Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆563Updated last month
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆106Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆139Updated last week
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆384Updated last week
• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆215Updated 3 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆179Updated 5 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆303Updated last year
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 5 months ago
• Avnet / hdl
  ☆111Updated 2 months ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 4 years ago
• ATaylorCEngFIET / MicroZed-Chronicles
  Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog
  ☆192Updated 6 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆137Updated last week
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆117Updated 6 years ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆243Updated last month