A configurable C++ generator of pipelined Verilog FFT cores
☆258Apr 18, 2024Updated 2 years ago
Alternatives and similar repositories for dblclockfft
Users that are interested in dblclockfft are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Apr 15, 2024Updated 2 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆97Jan 31, 2023Updated 3 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆132Feb 11, 2021Updated 5 years ago
- R2FFT is a fully synthesizable verilog module for doing the FFT on an FPGA or ASIC.☆22Apr 30, 2019Updated 7 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆76Apr 24, 2020Updated 6 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆61May 24, 2026Updated 2 weeks ago
- Dual MikroBUS board for Upduino 2 FPGA☆18May 24, 2018Updated 8 years ago
- Verilog modules for software-defined radio.☆20Dec 31, 2012Updated 13 years ago
- FFT algorithm for fpga☆25Aug 17, 2021Updated 4 years ago
- A collection of demonstration digital filters☆175Jan 18, 2024Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆121Jan 18, 2024Updated 2 years ago
- Cross EDA Abstraction and Automation☆41Nov 17, 2025Updated 6 months ago
- Verilog module for calculation of FFT.☆193Aug 22, 2012Updated 13 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A series of CORDIC related projects☆125Nov 12, 2024Updated last year
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 8 years ago
- A utility for Composing FPGA designs from Peripherals☆188Dec 23, 2024Updated last year
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆48May 20, 2021Updated 5 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- A basic Soft(Gate)ware Defined Radio architecture☆103Jan 18, 2024Updated 2 years ago
- Guitar Hero: Fast Fourier Edition. An MIT 6.111 final project that uses the power of the FPGA to play guitar hero with real guitars.☆13Dec 11, 2015Updated 10 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- DVI video out example for prjtrellis☆17Jan 20, 2019Updated 7 years ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 3 years ago
- Bus bridges and other odds and ends☆676Jun 2, 2026Updated last week
- Verilog AXI stream components for FPGA implementation☆893Feb 27, 2025Updated last year
- A Python toolbox for building complex digital hardware☆1,325Jan 5, 2026Updated 5 months ago
- Documenting the Anlogic FPGA bit-stream format.☆90Dec 25, 2022Updated 3 years ago
- Pipeline FFT Implementation in Verilog HDL☆168Apr 14, 2019Updated 7 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Synthesizable FIR filters in VHDL☆14Jul 19, 2019Updated 6 years ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,417May 10, 2026Updated 3 weeks ago
- Code generation tool for control and status registers☆463May 30, 2026Updated last week
- Common SystemVerilog components☆755Updated this week
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆62Jul 5, 2022Updated 3 years ago
- Small footprint and configurable DRAM core☆505Jun 2, 2026Updated last week