Alternatives and similar repositories for ethernet_tri_mode

Users that are interested in ethernet_tri_mode are comparing it to the libraries listed below

• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• freecores / pci
  PCI bridge
  ☆20Updated 11 years ago
• freecores / udp_ip_stack
  1G eth UDP / IP Stack
  ☆10Updated 11 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆22Updated 6 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• freecores / reed_solomon_decoder
  Reed Solomon Decoder (204,188)
  ☆12Updated 11 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆35Updated 4 years ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆13Updated 4 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆24Updated 11 years ago
• freecores / pipelined_fft_64
  Pipelined FFT/IFFT 64 points processor
  ☆11Updated 11 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆27Updated 4 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 11 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆17Updated last week
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆41Updated 4 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• ZipCPU / wbsata
  Wishbone SATA Controller
  ☆23Updated 2 months ago
• freecores / uart16550
  UART 16550 core
  ☆38Updated 11 years ago
• shalan / MS_QSPI_XIP_CACHE
  AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
  ☆14Updated 2 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆12Updated 5 years ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆12Updated 2 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 8 years ago
• freecores / i2cslave
  I2C Slave
  ☆14Updated 11 years ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆13Updated 9 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• freecores / simple_spi
  SPI core
  ☆12Updated 11 years ago
• freecores / 1000base-x
  1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)
  ☆22Updated 11 years ago