10_100_1000 Mbps tri-mode ethernet MAC
☆10Jul 17, 2014Updated 11 years ago
Alternatives and similar repositories for ethernet_tri_mode
Users that are interested in ethernet_tri_mode are comparing it to the libraries listed below
Sorting:
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Wishbone SATA Controller☆25Oct 16, 2025Updated 4 months ago
- Reed Solomon Decoder (204,188)☆12Jul 17, 2014Updated 11 years ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 6 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Jul 17, 2014Updated 11 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- SHA3 (KECCAK)☆18Jul 17, 2014Updated 11 years ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- Reed Solomon Encoder and Decoder Digital IP☆21Jun 14, 2020Updated 5 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆24Jul 17, 2014Updated 11 years ago
- Ethernet MAC 10/100 Mbps☆84Oct 2, 2019Updated 6 years ago
- The PS-FPGA project (top level)☆24May 12, 2021Updated 4 years ago
- PID controller on an FPGA with custom RS232 addressing protocol.☆25Sep 7, 2021Updated 4 years ago
- A verilog implementation of MIPS ISA.☆18Jul 7, 2019Updated 6 years ago
- DVB-S2 LDPC Decoder☆29Jul 17, 2014Updated 11 years ago
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆27Mar 21, 2022Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆33Oct 31, 2021Updated 4 years ago
- round robin arbiter☆78Jul 17, 2014Updated 11 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆33Aug 7, 2021Updated 4 years ago
- A drum machine made using a Raspberry Pi.☆12Apr 19, 2021Updated 4 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- ARM-CPU implemented verilog☆29Jan 13, 2024Updated 2 years ago
- ☆33Jul 9, 2022Updated 3 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.…☆45Aug 11, 2014Updated 11 years ago
- Must-have verilog systemverilog modules☆37May 1, 2022Updated 3 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆53May 16, 2025Updated 9 months ago
- A simple BOOTP server to support and simplify UEFI application development☆14Oct 24, 2016Updated 9 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- 使用Cordic算法函数运算，在资源受限的设备上运行（如资源较少的FPGA、嵌入式MCU），避免了浮点运算、乘法、除法，只用移位和加法函数的 计算。☆11Mar 22, 2024Updated last year
- ROM built with CMake☆11Jan 24, 2023Updated 3 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- ☆13Aug 7, 2025Updated 7 months ago
- ☆12Feb 15, 2024Updated 2 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆14Nov 4, 2020Updated 5 years ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago