Alternatives and similar repositories for ethernet_tri_mode

Users that are interested in ethernet_tri_mode are comparing it to the libraries listed below

• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 11 years ago
• freecores / pci
  PCI bridge
  ☆20Updated 11 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 11 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• freecores / mips_16
  Educational 16-bit MIPS Processor
  ☆17Updated 6 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• freecores / udp_ip_stack
  1G eth UDP / IP Stack
  ☆10Updated 11 years ago
• freecores / reed_solomon_decoder
  Reed Solomon Decoder (204,188)
  ☆12Updated 11 years ago
• freecores / i2cslave
  I2C Slave
  ☆14Updated 11 years ago
• ZipCPU / wbsata
  Wishbone SATA Controller
  ☆22Updated last month
• shalan / MS_QSPI_XIP_CACHE
  AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
  ☆13Updated 2 years ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 8 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• freecores / simple_spi
  SPI core
  ☆12Updated 11 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆17Updated 2 weeks ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆24Updated 11 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆32Updated 2 months ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆12Updated 4 years ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆14Updated 8 months ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆22Updated 6 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆32Updated 7 years ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆12Updated 2 years ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆13Updated 4 years ago
• wnew / hdl_library
  A library of verilog and vhdl modules
  ☆15Updated 7 years ago
• freecores / uart2spi
  UART To SPI
  ☆19Updated 11 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆18Updated 4 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 11 years ago