lvzhengde / xge-ptpv2
用于10G以太网的PTPv2硬件引擎设计,Verilog HDL描述
☆14Updated 8 months ago
Related projects: ⓘ
- 用于时间敏感网络TSN(Time-Sensitive Network)的SoC设计☆11Updated this week
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆40Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆38Updated 2 years ago
- FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆27Updated 2 months ago
- SPI-Flash XIP Interface (Verilog)☆36Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- ☆25Updated 2 years ago
- ☆16Updated 5 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆60Updated 3 months ago
- FPGA和USB3.0桥片实现USB3.0通信☆49Updated 2 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆25Updated 3 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆15Updated 4 years ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆14Updated 6 months ago
- DMA core compatible with AHB3-Lite☆9Updated 5 years ago
- An Ethernet MAC conforming to IEEE 802.3☆16Updated 7 years ago
- ☆18Updated 8 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆15Updated 5 years ago
- Hardware Assisted IEEE 1588 IP Core☆22Updated 10 years ago
- ☆16Updated 2 years ago
- FIR,FFT based on Verilog☆13Updated 6 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- 基于FPGA的FFT☆11Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆17Updated 4 years ago
- ☆12Updated 3 years ago
- IP Cores that can be used within Vivado☆24Updated 3 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆10Updated 3 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆20Updated 6 years ago