Alternatives and similar repositories for DPLL-FPGA:

Users that are interested in DPLL-FPGA are comparing it to the libraries listed below

• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆49Updated 2 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆69Updated 2 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆51Updated 8 months ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆25Updated 5 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆44Updated 3 years ago
• Muhazam-Mustapha / SqrtCORDIC
  A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.
  ☆15Updated 3 years ago
• erbanhun / ZTE_DPD
  ☆11Updated 6 years ago
• ankitshah009 / High-Radix-Adaptive-CORDIC
  High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC
  ☆13Updated 8 years ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆62Updated 2 years ago
• maxs-well / USB_Ctrl
  USB2.0 Verilog
  ☆17Updated 5 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆30Updated 4 years ago
• Starrynightzyq / Delta-Sigma-Modulator
  Delta-Sigma modulator (DSM) for fractional phase locked loop.
  ☆27Updated 3 years ago
• BigPig-Bro / Cyclone-IV
  【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板
  ☆21Updated 3 weeks ago
• filipamator / adpll
  All digital PLL
  ☆28Updated 7 years ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆23Updated 6 months ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆49Updated 10 years ago
• shinde-shantanu / FPGA_TDC
  Time to Digital Converter on an FPGA
  ☆14Updated 4 years ago
• Aperture-Electronic / Realtime-Bicubic-16X-SuperResolution-IP
  APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS
  ☆22Updated 2 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• briansune / Delta-Sigma-DAC-Verilog
  Delta Sigma DAC FPGA
  ☆37Updated last month
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆63Updated 3 years ago
• rumengshanhe / ADPLL_base_Verilog
  基于Verilog实现的全数字锁相环
  ☆26Updated 3 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆58Updated 3 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆51Updated 4 years ago
• vladniculescu / High-Speed-FPGA-based-Data-Acquisition-System-100MSPS
  ☆17Updated last year
• maxs-well / ad7606-driver-verilog
  AD7606 driver verilog
  ☆39Updated 5 years ago
• marsohod4you / FpgaTDC
  Project: Precise Measure of time delays in FPGA
  ☆29Updated 7 years ago
• ericgineer / CORDIC
  The CORDIC algorithm implemented in Octave/MATLAB and Verilog
  ☆29Updated 10 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆33Updated 3 years ago
• maxs-well / LMS-sound-filtering-by-Verilog
  LMS sound filtering by Verilog
  ☆39Updated 4 years ago