Alternatives and similar repositories for DPLL-FPGA

Users that are interested in DPLL-FPGA are comparing it to the libraries listed below

• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆72Updated 3 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆47Updated last week
• maxs-well / ad7606-driver-verilog
  AD7606 driver verilog
  ☆43Updated 6 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆53Updated 2 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆52Updated 11 years ago
• ankitshah009 / High-Radix-Adaptive-CORDIC
  High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC
  ☆14Updated 9 years ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆27Updated 5 years ago
• Aperture-Electronic / Realtime-Bicubic-16X-SuperResolution-IP
  APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS
  ☆24Updated 2 years ago
• BigPig-Bro / Gowin
  【例程】国产高云FPGA 开发板及其工程
  ☆33Updated 10 months ago
• DeamonYang / FPGA_SDR
  软件无线电，使用FPGA进行正交解调。
  ☆22Updated 6 years ago
• Hello-FPGA / ZYNQ7020_Core_Board
  This is xc7z020clg400 FPGA hardware core board design
  ☆58Updated last year
• BigPig-Bro / Cyclone-IV
  【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板
  ☆26Updated last month
• erbanhun / ZTE_DPD
  ☆11Updated 7 years ago
• Muhazam-Mustapha / SqrtCORDIC
  A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.
  ☆17Updated 4 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆65Updated 3 years ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆31Updated 10 months ago
• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆62Updated 10 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆64Updated last year
• jobisoft / jTDC
  FPGA based 30ps RMS TDCs
  ☆86Updated 7 years ago
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆30Updated 4 years ago
• filipamator / adpll
  All digital PLL
  ☆28Updated 7 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆49Updated 4 years ago
• maxs-well / USB_Ctrl
  USB2.0 Verilog
  ☆17Updated 6 years ago
• rumengshanhe / ADPLL_base_Verilog
  基于Verilog实现的全数字锁相环
  ☆38Updated 3 years ago
• amoudgl / iir-bandstop-filter
  Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
  ☆31Updated 8 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆70Updated 3 years ago
• maxs-well / LMS-sound-filtering-by-Verilog
  LMS sound filtering by Verilog
  ☆40Updated 5 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆19Updated this week
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆19Updated 6 years ago
• lulinchen / face_detect_open
  A Voila-Jones face detector hardware implementation
  ☆32Updated 6 years ago