AlbertYang0112 / DPLL-FPGALinks
A digital phase-locked loop implemented on Spartan-6
☆13Updated 6 years ago
Alternatives and similar repositories for DPLL-FPGA
Users that are interested in DPLL-FPGA are comparing it to the libraries listed below
Sorting:
- High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC☆13Updated 8 years ago
- ☆11Updated 7 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆71Updated 3 years ago
- FIR filter implementation☆27Updated 5 years ago
- All digital PLL☆28Updated 7 years ago
- LMS sound filtering by Verilog☆39Updated 5 years ago
- USB2.0 Verilog☆17Updated 6 years ago
- 基于Verilog实现的全数字锁相环☆36Updated 3 years ago
- 基于FPGA的FFT☆18Updated 6 years ago
- 【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板☆25Updated last week
- FPGA Technology Exchange Group相关文件管理☆45Updated 2 months ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆47Updated 4 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆17Updated 3 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆30Updated 4 years ago
- An open-source Verilog implementation of Serial Peripheral Interface protocol with simulation support for efficient data exchange.☆13Updated last year
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆26Updated 9 months ago
- Reed Solomon Encoder and Decoder Digital IP☆21Updated 5 years ago
- FPGA纯逻辑实现modbus通信☆20Updated 2 years ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆22Updated 2 years ago
- 软件无线电,使用FPGA进行正交解调。☆22Updated 6 years ago
- AD7606 driver verilog☆42Updated 6 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆57Updated 11 months ago
- Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC☆26Updated 7 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆55Updated 4 years ago
- configurable cordic core in verilog☆51Updated 10 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 4 years ago
- My code repositry for common use.☆22Updated 3 years ago
- FPGA based 30ps RMS TDCs☆84Updated 7 years ago
- 【例程】国产高云FPGA 开发板及其工程☆28Updated 8 months ago