AlbertYang0112 / DPLL-FPGA
A digital phase-locked loop implemented on Spartan-6
☆13Updated 6 years ago
Alternatives and similar repositories for DPLL-FPGA
Users that are interested in DPLL-FPGA are comparing it to the libraries listed below
Sorting:
- High Radix Adaptive CORDIC Algorithm - Improvement over Traditional CORDIC☆13Updated 8 years ago
- ☆11Updated 7 years ago
- All digital PLL☆28Updated 7 years ago
- FIR filter implementation☆26Updated 5 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆17Updated 3 years ago
- 【例程】简单的FPGA入门项目 适用于各类Cyclone 开发板☆21Updated 2 months ago
- 基于Verilog实现的全数字锁相环☆31Updated 3 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆70Updated 2 years ago
- An open-source Verilog implementation of Serial Peripheral Interface protocol with simulation support for efficient data exchange.☆13Updated last year
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆28Updated 3 years ago
- FPGA Technology Exchange Group相关文件管理☆44Updated last month
- USB2.0 Verilog☆17Updated 6 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆24Updated 7 months ago
- APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS☆22Updated 2 years ago
- configurable cordic core in verilog☆49Updated 10 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 4 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆55Updated 10 months ago
- 基于FPGA的FFT☆16Updated 6 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆46Updated 3 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆49Updated 3 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆53Updated 4 years ago
- Must-have verilog systemverilog modules☆34Updated 3 years ago
- FPGA 同步FIFO与异步FIFO☆30Updated 6 years ago
- 软件无线电,使用FPGA进行正交解调。☆21Updated 6 years ago
- FPGA纯逻辑实现modbus通信☆18Updated 2 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆32Updated 6 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆64Updated 3 years ago
- AD7606 driver verilog☆40Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆32Updated 5 years ago