JakeMercer / mac
An Ethernet MAC conforming to IEEE 802.3
☆16Updated 7 years ago
Related projects ⓘ
Alternatives and complementary repositories for mac
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Ethernet 10GE MAC☆44Updated 10 years ago
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆17Updated 10 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Verification of Ethernet Switch System Verilog☆11Updated 8 years ago
- ☆16Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 4 years ago
- Extensible FPGA control platform☆54Updated last year
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆63Updated this week
- DDR3 SDRAM controller☆18Updated 10 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Implementation of the PCIe physical layer☆30Updated last week
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆29Updated last year
- Platform Level Interrupt Controller☆35Updated 6 months ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- ☆23Updated 3 years ago
- Revision Control Labs and Materials☆23Updated 6 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆15Updated 6 years ago
- JTAG Test Access Port (TAP)☆30Updated 10 years ago
- ☆20Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆39Updated 7 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago