ZipCPU / interpolationLinks
Digital Interpolation Techniques Applied to Digital Signal Processing
☆67Updated last year
Alternatives and similar repositories for interpolation
Users that are interested in interpolation are comparing it to the libraries listed below
Sorting:
- A collection of phase locked loop (PLL) related projects☆115Updated last year
- A series of CORDIC related projects☆120Updated last year
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- A collection of demonstration digital filters☆162Updated last year
- Extensible FPGA control platform☆61Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆67Updated 3 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆72Updated last month
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆100Updated this week
- Testbenches for HDL projects☆22Updated last week
- Wishbone to AXI bridge (VHDL)☆44Updated 6 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆126Updated 4 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 10 months ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆112Updated 9 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- VHDL Modules☆24Updated 10 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- Verilog Repository for GIT☆35Updated 4 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆82Updated 4 years ago