ZipCPU / interpolation
Digital Interpolation Techniques Applied to Digital Signal Processing
☆59Updated 9 months ago
Alternatives and similar repositories for interpolation:
Users that are interested in interpolation are comparing it to the libraries listed below
- A collection of phase locked loop (PLL) related projects☆103Updated last year
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Verilog digital signal processing components☆131Updated 2 years ago
- Extensible FPGA control platform☆59Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆43Updated 9 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆55Updated 2 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- Gaussian noise generator Verilog IP core☆30Updated last year
- RISCV model for Verilator/FPGA targets☆50Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆33Updated 3 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated 11 months ago
- A series of CORDIC related projects☆99Updated 4 months ago
- UART -> AXI Bridge☆60Updated 3 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 7 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆40Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Wishbone controlled I2C controllers☆47Updated 4 months ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated last month
- ☆26Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- A collection of demonstration digital filters☆148Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago