ZipCPU/interpolation external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

ZipCPU/interpolation

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/ZipCPU/interpolation)

Close

ZipCPU / interpolationView on GitHubMore

• External links
• Readme badge

Digital Interpolation Techniques Applied to Digital Signal Processing

☆70Jun 24, 2024Updated 2 years ago

Alternatives and similar repositories for interpolation

Users that are interested in interpolation are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• ZipCPU / dspfilters

  View on GitHub
  A collection of demonstration digital filters
  ☆179Jan 18, 2024Updated 2 years ago
• freecores / wdsp

  View on GitHub
  DSP WishBone Compatible Cores
  ☆14Jul 17, 2014Updated 12 years ago
• ramanmangla / Digital-Audio-Equalizer

  View on GitHub
  Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.
  ☆12Aug 9, 2019Updated 7 years ago
• regymm / ymmcu-ft2232

  View on GitHub
  FT2232HL JTAG & UART Downloader
  ☆22Jul 18, 2021Updated 5 years ago
• DaveBerkeley / fpga

  View on GitHub
  Verilog FPGA code : including experimental DSP audio processor
  ☆14Dec 1, 2020Updated 5 years ago
• Managed Database hosting by DigitalOcean • Ad
  PostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
• freecores / ethernet_tri_mode

  View on GitHub
  10_100_1000 Mbps tri-mode ethernet MAC
  ☆11Jul 17, 2014Updated 12 years ago
• freecores / wb_dma

  View on GitHub
  WISHBONE DMA/Bridge IP Core
  ☆18Jul 17, 2014Updated 12 years ago
• ahmedshahein / DSP-RTL-Lib

  View on GitHub
  RTL Verilog library for various DSP modules
  ☆101Feb 17, 2022Updated 4 years ago
• controlpaths / cp_som_one

  View on GitHub
  Artix7 SOM
  ☆22Sep 9, 2024Updated last year
• sabpprook / AmaneroOemToolBypass

  View on GitHub
  A loader to bypass firmware flashing authentication on cloned Amanero Combo384 USB card
  ☆16Mar 16, 2026Updated 5 months ago
• analogdevicesinc / testbenches

  View on GitHub
  Testbenches for HDL projects
  ☆23Updated this week
• freecores / mips_16

  View on GitHub
  Educational 16-bit MIPS Processor
  ☆18Feb 16, 2019Updated 7 years ago
• Zeba-Xie / Open-USB2.0-Device-Controller

  View on GitHub
  USB2.0 Device Controller IP Core
  ☆19Aug 18, 2023Updated 3 years ago
• mballance / fwrisc-s

  View on GitHub
  ☆10Nov 8, 2019Updated 6 years ago
• Managed hosting for WordPress and PHP on Cloudways • Ad
  Managed hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
• ZipCPU / qoiimg

  View on GitHub
  Quite OK image compression Verilog implementation
  ☆24Nov 27, 2024Updated last year
• fengyulin1996 / Verilog-DSP

  View on GitHub
  FIR，FFT based on Verilog
  ☆14Dec 3, 2017Updated 8 years ago
• Evrytania / Matlab-Library

  View on GitHub
  Matlab functions for wireless communications focussing mostly on LTE / 3GPP.
  ☆49Aug 20, 2012Updated 14 years ago
• Minres / RDL-Editor

  View on GitHub
  A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
  ☆12Feb 9, 2024Updated 2 years ago
• akhan3 / async-fifo

  View on GitHub
  Asynchronous FIFO for transferring data between two asynchronous clock domains
  ☆17Jun 3, 2016Updated 10 years ago
• www-asics-ws / wb_conmax

  View on GitHub
  WISHBONE Interconnect
  ☆11Oct 1, 2017Updated 8 years ago
• coflery / STM32F4_USB_SoundCard

  View on GitHub
  fork from https://gitee.com/crouchggj/STM32F4_USB_SoundCard
  ☆17Aug 3, 2019Updated 7 years ago
• ZipCPU / dpll

  View on GitHub
  A collection of phase locked loop (PLL) related projects
  ☆122Jan 18, 2024Updated 2 years ago
• redchenjs / neopixel_led_controller_max10

  View on GitHub
  NeoPixel LED Controller | NeoPixel LED 控制器 | 基於MAX10 FPGA的音樂全彩光立方LED控制器
  ☆12Jan 4, 2022Updated 4 years ago
• Wordpress hosting with auto-scaling - Free Trial Offer • Ad
  Fully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
• adafruit / Adafruit-IS31FL3731-CharliePlex-LED-Breakout-PCB

  View on GitHub
  PCB files for the IS31FL3731 CharliePlex LED Breakouts
  ☆10Dec 21, 2022Updated 3 years ago
• evanfrazierc / FPGA-MP3-Player

  View on GitHub
  ☆13Oct 20, 2015Updated 10 years ago
• ultraembedded / core_ulpi_wrapper

  View on GitHub
  ULPI Link Wrapper (USB Phy Interface)
  ☆38May 3, 2020Updated 6 years ago
• theseus-cores / theseus-cores

  View on GitHub
  Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)
  ☆16Aug 16, 2021Updated 5 years ago
• tomverbeure / usb_system

  View on GitHub
  SpinalHDL USB system for the ULPI based Arrow DECA board
  ☆20Jan 9, 2022Updated 4 years ago
• alexforencich / verilog-dsp

  View on GitHub
  Verilog digital signal processing components
  ☆191Oct 30, 2022Updated 3 years ago
• conandllu / USB_Interface

  View on GitHub
  USB audio interface,design by STM32 and EP4CE6 FPGA,support DSD
  ☆16Jan 20, 2017Updated 9 years ago
• davidcastells / py4hw

  View on GitHub
  Hardware Design/Visualization/Simulation/RTLGeneration Framework
  ☆18Jul 30, 2026Updated last month
• jouyang3 / FMCW

  View on GitHub
  Miniature 8GHz FMCW Radar
  ☆12Mar 29, 2016Updated 10 years ago
• End-to-end encrypted cloud storage - Proton Drive • Ad
  Special offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
• ghz-ws / fpga_dsp_old

  View on GitHub
  DSP by FPGA
  ☆15Sep 12, 2023Updated 2 years ago
• Des333 / soc-fpga2sdram-test

  View on GitHub
  Testing FPGA2SDRAM interface on Altera Cyclone V SoC
  ☆14May 12, 2015Updated 11 years ago
• rbarzic / ml-ahb-gen

  View on GitHub
  A Verilog AMBA AHB Multilayer interconnect generator
  ☆13Aug 8, 2017Updated 9 years ago
• freecores / wb_builder

  View on GitHub
  WISHBONE Builder
  ☆15Sep 10, 2016Updated 9 years ago
• subutai-attic / pars

  View on GitHub
  ☆31Apr 1, 2017Updated 9 years ago
• grayresearch / xsoc-xr16

  View on GitHub
  Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…
  ☆13Jan 7, 2023Updated 3 years ago
• borgestrand / winuac2

  View on GitHub
  Open Source Windows UAC2 driver
  ☆21Feb 24, 2013Updated 13 years ago