MorrisMA / 1PPS-DPLLLinks
DPLL for phase-locking to 1PPS signal
☆34Updated 9 years ago
Alternatives and similar repositories for 1PPS-DPLL
Users that are interested in 1PPS-DPLL are comparing it to the libraries listed below
Sorting:
- A collection of phase locked loop (PLL) related projects☆116Updated 2 years ago
- Simple UART controller for FPGA written in VHDL☆105Updated 4 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Verilog wishbone components☆124Updated 2 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆127Updated 4 years ago
- Nitro USB FPGA core☆86Updated last year
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆86Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- A series of CORDIC related projects☆121Updated last year
- Small (Q)SPI flash memory programmer in Verilog☆68Updated 3 years ago
- Wishbone controlled I2C controllers☆57Updated last year
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆114Updated 9 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- Basic USB-CDC device core (Verilog)☆86Updated 4 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Updated 5 years ago
- A collection of demonstration digital filters☆166Updated 2 years ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆72Updated 8 years ago
- A wishbone controlled scope for FPGA's☆87Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆115Updated last week
- Open-source high performance AXI4-based HyperRAM memory controller☆82Updated 3 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆45Updated 4 years ago
- VHDL Modules☆24Updated 10 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆78Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆40Updated 11 months ago
- Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA☆73Updated 5 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Updated 8 years ago
- assorted library of utility cores for amaranth HDL☆102Updated last year
- ☆89Updated 8 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago