Implementation of the PCIe physical layer
☆64Jul 11, 2025Updated last year
Alternatives and similar repositories for PCIe-Physical-Layer
Users that are interested in PCIe-Physical-Layer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PCIE 5.0 Graduation project (Verification Team)☆107Jan 27, 2024Updated 2 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- PCI Express ® Base Specification Revision 3.0☆13May 23, 2018Updated 8 years ago
- ☆89Jun 27, 2022Updated 4 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆25Jul 6, 2018Updated 8 years ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆90Mar 21, 2024Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- Verilog PCI express components☆1,652Apr 26, 2024Updated 2 years ago
- ☆12May 8, 2022Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆46Jan 6, 2023Updated 3 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆300Mar 26, 2022Updated 4 years ago
- ☆14Jun 30, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- VIP for AXI Protocol☆185May 24, 2022Updated 4 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM☆18Aug 19, 2026Updated 2 weeks ago
- pcie-bench code for NetFPGA/VCU709 cards☆46Jul 27, 2018Updated 8 years ago
- General Purpose AXI Direct Memory Access☆80May 12, 2024Updated 2 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Direct Access Memory for MPSoC☆13Aug 7, 2026Updated 3 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- The memory model was leveraged from micron.☆32Mar 24, 2018Updated 8 years ago
- AXI Interconnect☆58Aug 20, 2021Updated 5 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- Verification IP for APB protocol☆80Dec 18, 2020Updated 5 years ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆149Jun 16, 2026Updated 2 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 8 years ago
- ☆82Feb 4, 2021Updated 5 years ago
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆39Aug 24, 2026Updated last week
- ☆23Mar 19, 2026Updated 5 months ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆29Jan 28, 2025Updated last year
- DDR2 memory controller written in Verilog☆86Feb 28, 2012Updated 14 years ago
- USB3 PIPE interface for Xilinx 7-Series☆270Apr 3, 2026Updated 5 months ago