Xilinx / SDFEC-PYNQLinks
A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC
☆13Updated 2 years ago
Alternatives and similar repositories for SDFEC-PYNQ
Users that are interested in SDFEC-PYNQ are comparing it to the libraries listed below
Sorting:
- Board repo for the ZCU216 RFSOC☆28Updated 2 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆28Updated 2 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆32Updated 2 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆39Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆103Updated 2 years ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆62Updated 4 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆24Updated last year
- ☆19Updated 3 years ago
- Demonstration of Automatic Gain Control with PYNQ☆14Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆79Updated 11 months ago
- Board files to build the ZCU111 PYNQ image☆19Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆19Updated 6 months ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆49Updated 2 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆23Updated 3 years ago
- Python productivity for RFSoC platforms☆72Updated last year
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆37Updated 2 years ago
- Various utilities for working with FPGAs☆13Updated 9 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆26Updated 4 years ago
- ☆38Updated last month
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆61Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆54Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- ☆18Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 3 months ago
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago