VSD workshop - Phase Locked Loop(PLL) IC Design
☆17Aug 4, 2021Updated 4 years ago
Alternatives and similar repositories for Phase-locked-loop-IC-design
Users that are interested in Phase-locked-loop-IC-design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆21Feb 16, 2022Updated 4 years ago
- 8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving…☆15Jul 21, 2022Updated 4 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆32Feb 21, 2019Updated 7 years ago
- Open Analog Design Environment☆26May 19, 2023Updated 3 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆94Jun 12, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- All Digital Phase-Locked Loop☆14May 22, 2023Updated 3 years ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 5 years ago
- Wi-Fi enabled XVC programmer/debugger based on ESP8266☆12May 31, 2015Updated 11 years ago
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆13Feb 2, 2022Updated 4 years ago
- All-Digital Phase-Locked Loops (ADPLL) code in High Speed Integrated Circuit Hardware Description Language (VHDL) for a Field Programmabl…☆13Oct 20, 2025Updated 9 months ago
- Generate testbench for your verilog module.☆12Sep 12, 2018Updated 7 years ago
- Imagination Technologies Catapult SDK RISC-V Software Development Kit☆12Oct 18, 2024Updated last year
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- Implementation of a fully-functional digital signal oscilloscope written in Verilog HDL. Tested on a DE-1 SoC 5CSEMA5F31C6 FPGA board. Us…☆25Aug 25, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.☆24Sep 21, 2021Updated 4 years ago
- PAST SHORT COURSES AND TUTORIALS FROM ISSCC.☆17Apr 7, 2024Updated 2 years ago
- Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.☆10Jul 12, 2023Updated 3 years ago
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- ☆13Apr 12, 2023Updated 3 years ago
- the demo codes for New Concept C Language☆13May 14, 2014Updated 12 years ago
- Zero to ASIC group submission for MPW2☆13Mar 26, 2025Updated last year
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆14Nov 4, 2020Updated 5 years ago
- Verilog ADC interface for adc128s022 found in De0 Nano☆15Jul 7, 2015Updated 11 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Basic Simulink Blocks for modeling CDRs and PLLs☆16Apr 25, 2020Updated 6 years ago
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆17Apr 27, 2026Updated 3 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 4 years ago
- pcells for various magnetic passive devices (GPL v3)☆13Sep 21, 2013Updated 12 years ago
- Local RF control of Dreo CLF513S ceiling fan☆15Jun 24, 2026Updated last month
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆44Jun 6, 2021Updated 5 years ago
- python with flask☆10Jun 26, 2020Updated 6 years ago
- This project offers an improved, redesigned and cleaned fork of the original sources.☆15Jan 29, 2016Updated 10 years ago
- This is a complementary extension to the https://hub.docker.com/r/hpretl/iic-osic-tools Docker image, adding support for RF simulations a…☆17Apr 6, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆13Jul 8, 2019Updated 7 years ago
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆15Apr 14, 2026Updated 3 months ago
- Implements NCurses Disk Usage(ncdu) with golang☆44Jul 10, 2023Updated 3 years ago
- Python package for design and simulation of RF phase-locked loops☆15Apr 23, 2022Updated 4 years ago
- Cadence Virtuoso Design Management System☆39Nov 13, 2022Updated 3 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆25Jan 20, 2021Updated 5 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 8 years ago