abhishek-kakkar / 100DayFPGA
Scratchpad repository for the 100-day FPGA challenge
☆14Updated 5 years ago
Alternatives and similar repositories for 100DayFPGA:
Users that are interested in 100DayFPGA are comparing it to the libraries listed below
- ☆30Updated 4 years ago
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated 11 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- Extensible FPGA control platform☆59Updated last year
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆72Updated 3 years ago
- SAR ADC on tiny tapeout☆39Updated 2 months ago
- An example of analogue design using open source IC design tools☆29Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆40Updated last year
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆59Updated 3 years ago
- understanding the tinyfpga bootloader☆24Updated 6 years ago
- ☆33Updated 2 years ago
- ☆45Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆110Updated 3 years ago
- Wishbone controlled I2C controllers☆47Updated 4 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Collection of projects for various FPGA development boards☆44Updated 10 months ago
- Small footprint and configurable JESD204B core☆41Updated 2 months ago
- ☆20Updated 2 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated last month
- ☆44Updated 2 weeks ago
- RISCV SoftCPU Contest 2018☆14Updated 6 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆24Updated last month