aniket0511 / Sigmoid-FunctionLinks
Hardware Implementation of Sigmoid Function using verilog HDL
☆15Updated 5 years ago
Alternatives and similar repositories for Sigmoid-Function
Users that are interested in Sigmoid-Function are comparing it to the libraries listed below
Sorting:
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆55Updated last year
- A collection of commonly asked RTL design interview questions☆36Updated 8 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆24Updated last year
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- Some useful documents of Synopsys☆90Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆135Updated 7 years ago
- UVM and System Verilog Manuals☆45Updated 6 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated 2 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Updated 8 years ago
- ☆37Updated 6 years ago
- Asynchronous fifo in verilog☆37Updated 9 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆40Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆95Updated 6 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆83Updated 7 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆171Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆101Updated 2 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆70Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆180Updated 2 months ago
- VIP for AXI Protocol☆158Updated 3 years ago
- 3×3脉动阵列乘法器☆48Updated 6 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- ☆14Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆21Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆31Updated 3 months ago