aniket0511 / Sigmoid-Function
Hardware Implementation of Sigmoid Function using verilog HDL
☆15Updated 5 years ago
Alternatives and similar repositories for Sigmoid-Function:
Users that are interested in Sigmoid-Function are comparing it to the libraries listed below
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Updated 5 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆49Updated 4 years ago
- ☆31Updated 5 years ago
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆82Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆31Updated last year
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆94Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆29Updated 4 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- Template for project1 TPU☆18Updated 3 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆28Updated 4 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆29Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆16Updated 11 months ago
- ☆16Updated last week
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- AIChip 2021 project, NCKU☆17Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 7 months ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆12Updated 6 years ago