Hardware Implementation of Sigmoid Function using verilog HDL
☆16Dec 16, 2019Updated 6 years ago
Alternatives and similar repositories for Sigmoid-Function
Users that are interested in Sigmoid-Function are comparing it to the libraries listed below
Sorting:
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 5 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 3 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated 9 months ago
- autonomous driving contest reference kit☆10Dec 2, 2021Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Jan 12, 2021Updated 5 years ago
- Submission template for Tiny Tapeout 6 - Verilog HDL Projects☆35May 3, 2024Updated last year
- OpenTitan FI formal verification framework☆16Aug 29, 2023Updated 2 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- sailVina用于Linux的反向对接脚本☆10Feb 14, 2021Updated 5 years ago
- We open-source our layout level fast EM simulation tool, EMSim, to the public.☆14Feb 8, 2024Updated 2 years ago
- ☆10Aug 22, 2023Updated 2 years ago
- ☆15Sep 24, 2023Updated 2 years ago
- 在python框架下，搭建简单三层(20,3,3)BP神经网络,通过对音频的MFCC系数的特征最大值进行学习，在较少训练次数下，实现对三个人音频信号的识别。☆11Jun 9, 2019Updated 6 years ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆13Jan 28, 2019Updated 7 years ago
- ☆14Jul 20, 2020Updated 5 years ago
- ☆10Jun 3, 2020Updated 5 years ago
- NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道三等奖☆14Aug 17, 2024Updated last year
- Sparse Multilabel Categorical Crossentropy☆11Sep 10, 2023Updated 2 years ago
- A innovative IME core enabling seamless cross-typing among multiple input methods.☆16Aug 12, 2025Updated 6 months ago
- Automatically set the primary video output at boot-time given a video device is unavailable due to hardware-passthrough (VFIO), or any ot…☆13Jun 5, 2025Updated 9 months ago
- My notes for getting ROS2 running on raspberry pi zero w☆12Aug 10, 2018Updated 7 years ago
- ☆15Mar 25, 2020Updated 5 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆14Jul 23, 2020Updated 5 years ago
- Raspberry Pi cluster with OpenMPI☆14May 13, 2017Updated 8 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- ☆17Nov 14, 2022Updated 3 years ago
- Multi Layer Perceptron by Vivado HLS for Xilinx FPGA implementation☆12Dec 26, 2016Updated 9 years ago
- Facial Landmark Detection using OpenCV and Mediapipe☆12Jul 4, 2022Updated 3 years ago
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- ☆11Dec 31, 2019Updated 6 years ago
- raid is a GDB-like tiny debugger which is based on ptrace.☆16Jul 27, 2022Updated 3 years ago
- A novel BCI-based messaging web application that uses P300 speller and emotion detection to bridge the gap in social media accessibility …☆12Aug 31, 2021Updated 4 years ago
- My Solution to chapter exercises for Digital Design 6e - With Introduction to The Verilog HDL, VHDL and System Verilog☆15Mar 12, 2020Updated 5 years ago
- Open hardware & software DIY spin coater☆17Dec 2, 2025Updated 3 months ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆15Feb 17, 2019Updated 7 years ago