adamgallas / FireFly-v1
[TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks with Efficient DSP and Memory Optimization"
☆16Updated 10 months ago
Alternatives and similar repositories for FireFly-v1:
Users that are interested in FireFly-v1 are comparing it to the libraries listed below
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆16Updated 9 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆32Updated last month
- Open-source of MSD framework☆16Updated last year
- ☆13Updated 9 months ago
- A co-design architecture on sparse attention☆51Updated 3 years ago
- ☆38Updated last year
- C++ code for HLS FPGA implementation of transformer☆15Updated 5 months ago
- ☆13Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆44Updated 5 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆34Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆48Updated this week
- ☆17Updated 3 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆12Updated 2 years ago
- ☆15Updated 9 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆45Updated last month
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- 关于移植模型至gemmini的文档☆21Updated 2 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆14Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆77Updated 3 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆24Updated 11 months ago
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆19Updated 2 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆26Updated last year
- ☆25Updated 2 months ago
- ☆100Updated 4 years ago
- ☆43Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆34Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆28Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆36Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆13Updated 7 months ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆121Updated last year