scratch-gpu / MIAOW2
MIAOW2.0 FPGA implementable design
☆12Updated 7 years ago
Alternatives and similar repositories for MIAOW2:
Users that are interested in MIAOW2 are comparing it to the libraries listed below
- ☆26Updated 4 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Reconfigurable Binary Engine☆16Updated 4 years ago
- ☆43Updated 6 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 7 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- RTL code of some arbitration algorithm☆13Updated 5 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆25Updated last week
- ☆26Updated 5 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆18Updated 11 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- ☆31Updated 5 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆37Updated 6 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- ☆25Updated last year
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆28Updated last year
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Updated 10 years ago