ebby-s / MX-for-FPGA
Implementation of Microscaling data formats in SystemVerilog.
☆14Updated 5 months ago
Alternatives and similar repositories for MX-for-FPGA:
Users that are interested in MX-for-FPGA are comparing it to the libraries listed below
- ☆25Updated last month
- Open-source of MSD framework☆16Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆47Updated 2 weeks ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆34Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆36Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆13Updated 7 months ago
- ☆21Updated this week
- A co-design architecture on sparse attention☆51Updated 3 years ago
- ☆19Updated last year
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆20Updated 2 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆46Updated 4 months ago
- MICRO22 artifact evaluation for Sparseloop☆41Updated 2 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆24Updated 11 months ago
- Official implementation of EMNLP'23 paper "Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?"☆19Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆42Updated last month
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆17Updated 10 months ago
- ☆39Updated 7 months ago
- ☆22Updated 2 years ago
- ☆12Updated last year
- ☆9Updated 2 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆68Updated 3 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆28Updated 6 months ago
- ☆43Updated 3 years ago
- ☆32Updated 4 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆23Updated 2 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆28Updated 3 weeks ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆18Updated 9 months ago
- ☆18Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆48Updated 3 weeks ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago