Alternatives and similar repositories for AES

Users that are interested in AES are comparing it to the libraries listed below

• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆49Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated 2 weeks ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• aignacio / mpsoc_example
  ☆60Updated 4 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 3 weeks ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆38Updated 2 weeks ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆73Updated 11 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆90Updated last month
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆51Updated 3 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆31Updated 5 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 4 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆21Updated 2 years ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆18Updated 7 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆31Updated 4 years ago
• olofk / vidbo
  Virtual Development Board
  ☆63Updated 3 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆31Updated 4 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆47Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆68Updated 2 months ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆22Updated 4 years ago