Alternatives and similar repositories for AES:

Users that are interested in AES are comparing it to the libraries listed below

• b224hisl / rioschip
  ☆33Updated 2 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆43Updated 2 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• andrewattwood / fuserisc
  Dual RISC-V DISC with integrated eFPGA
  ☆16Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆39Updated last year
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated last year
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆57Updated 2 weeks ago
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆15Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆56Updated 3 weeks ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆15Updated 3 years ago
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆31Updated last year
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• riscveval / Rocket-Chip
  ☆21Updated 7 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆52Updated last year
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆43Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆40Updated 3 months ago