Open-Source-Hardware-Initiative / AES
Open Source AES
☆31Updated 7 months ago
Related projects ⓘ
Alternatives and complementary repositories for AES
- ☆33Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 10 months ago
- Bitstream relocation and manipulation tool.☆40Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- A padring generator for ASICs☆22Updated last year
- Virtual development board for HDL design☆39Updated last year
- Demo SoC for SiliconCompiler.☆52Updated 3 weeks ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆20Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆16Updated last year
- Dual RISC-V DISC with integrated eFPGA☆15Updated 3 years ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated last month
- Benchmarks for Yosys development☆22Updated 4 years ago
- ☆57Updated 3 years ago
- Xilinx Unisim Library in Verilog☆71Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ☆36Updated 2 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆25Updated 5 years ago
- Source-Opened RISCV for Crypto☆15Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- A pipelined RISC-V processor☆48Updated 11 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 4 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆35Updated last year
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆47Updated this week
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆71Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago
- Flip flop setup, hold & metastability explorer tool☆31Updated 2 years ago