☆35Apr 20, 2021Updated 5 years ago
Alternatives and similar repositories for SpGEMM
Users that are interested in SpGEMM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- RTL implementation of Flex-DPE.☆119Feb 22, 2020Updated 6 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- RTL generator for SpGEMM☆13Feb 2, 2021Updated 5 years ago
- ☆14Feb 14, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- [ISCA'25] LIA: A Single-GPU LLM Inference Acceleration with Cooperative AMX-Enabled CPU-GPU Computation and CXL Offloading☆12Jun 28, 2025Updated last year
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆25Nov 9, 2025Updated 9 months ago
- a general-purpose machine learning-driven auto-tuner for heterogeneous platforms☆10Sep 7, 2024Updated last year
- Eyeriss chip simulator☆41Mar 6, 2020Updated 6 years ago
- eyeriss-chisel3☆40May 2, 2022Updated 4 years ago
- ☆17Apr 13, 2018Updated 8 years ago
- ordspecsim: The Swarm architecture simulator☆25Feb 15, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 7 years ago
- RISC-V SST CPU Component☆25Apr 15, 2026Updated 4 months ago
- Source code of the PPoPP '22 paper: "TileSpGEMM: A Tiled Algorithm for Parallel Sparse General Matrix-Matrix Multiplication on GPUs" by Y…☆48May 22, 2024Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- SDSoC example projects☆13Mar 13, 2021Updated 5 years ago
- pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel stori…☆20Jan 12, 2023Updated 3 years ago
- ☆671Jan 13, 2021Updated 5 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- ☆10Jun 28, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆13May 8, 2025Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆48Apr 4, 2022Updated 4 years ago
- ☆12Mar 14, 2023Updated 3 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆68Sep 24, 2021Updated 4 years ago
- A small Neural Network Processor for Edge devices.☆20Nov 22, 2022Updated 3 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- Parametric Integer Programming Library☆15Updated this week
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆132Mar 6, 2026Updated 5 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Apr 30, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Tutorial Material from the SST Team☆27Aug 5, 2025Updated last year
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆38Mar 14, 2021Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆28Aug 7, 2026Updated 3 weeks ago
- ☆10Jan 3, 2022Updated 4 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆211Jun 25, 2020Updated 6 years ago
- Ventus GPGPU ISA Simulator Based on Spike☆53Aug 20, 2026Updated last week