sld-columbia / hl5Links
A 32-bit RISC-V Processor Designed with High-Level Synthesis
☆54Updated 5 years ago
Alternatives and similar repositories for hl5
Users that are interested in hl5 are comparing it to the libraries listed below
Sorting:
- ☆87Updated last year
- DASS HLS Compiler☆29Updated last year
- Next generation CGRA generator☆114Updated this week
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆40Updated last month
- ☆60Updated last week
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆123Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Public release☆57Updated 6 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 3 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- ☆12Updated 3 weeks ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆86Updated 11 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- ILA Model Database☆23Updated 4 years ago
- ☆63Updated 4 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆61Updated 11 months ago
- The OpenPiton Platform☆29Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- ☆28Updated 7 years ago