sld-columbia / hl5
A 32-bit RISC-V Processor Designed with High-Level Synthesis
☆52Updated 5 years ago
Alternatives and similar repositories for hl5:
Users that are interested in hl5 are comparing it to the libraries listed below
- Tests for example Rocket Custom Coprocessors☆72Updated 5 years ago
- ☆87Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Project repo for the POSH on-chip network generator☆44Updated last year
- CGRA framework with vectorization support.☆27Updated last week
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 11 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆76Updated 11 months ago
- ☆57Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- Next generation CGRA generator☆109Updated this week
- ILA Model Database☆22Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- ☆15Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆121Updated last week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- ☆26Updated 7 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆63Updated this week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- DASS HLS Compiler☆29Updated last year
- An Open-Hardware CGRA for accelerated computation on the edge.☆21Updated 6 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- ☆15Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ☆57Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago