pc2 / HPCC_FPGALinks
A OpenCL-based FPGA benchmark suite for HPC
☆34Updated 6 months ago
Alternatives and similar repositories for HPCC_FPGA
Users that are interested in HPCC_FPGA are comparing it to the libraries listed below
Sorting:
- DASS HLS Compiler☆29Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16Updated 4 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- ☆30Updated 6 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- ☆58Updated 2 years ago
- A Comprehensive Model-Based Analysis Framework for High Level Synthesis of Real Applications☆37Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 3 weeks ago
- ☆87Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- ☆24Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Heterogeneous simulator for DECADES Project☆32Updated last year
- ☆36Updated 4 years ago
- MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)☆21Updated last year
- CGRA framework with vectorization support.☆35Updated this week
- ☆28Updated 7 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆29Updated 7 months ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 4 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated 2 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 3 weeks ago