pc2 / HPCC_FPGALinks
A OpenCL-based FPGA benchmark suite for HPC
☆34Updated 9 months ago
Alternatives and similar repositories for HPCC_FPGA
Users that are interested in HPCC_FPGA are comparing it to the libraries listed below
Sorting:
- DASS HLS Compiler☆29Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated last month
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆30Updated 6 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated this week
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ☆60Updated 2 years ago
- FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- ☆87Updated last year
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated 2 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Fast Floating Point Operators for High Level Synthesis☆21Updated 2 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Updated 5 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆24Updated 11 months ago
- ☆36Updated 4 years ago
- ☆29Updated 8 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago