intel / fpga-trainingLinks
☆33Updated last year
Alternatives and similar repositories for fpga-training
Users that are interested in fpga-training are comparing it to the libraries listed below
Sorting:
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆115Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- ☆87Updated last year
- A polyhedral compiler for hardware accelerators☆59Updated last year
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 3 weeks ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆97Updated 4 months ago
- Next generation CGRA generator☆115Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆75Updated 2 weeks ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆51Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 4 months ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆126Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- ☆59Updated 2 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.