intel / fpga-trainingLinks
☆34Updated last year
Alternatives and similar repositories for fpga-training
Users that are interested in fpga-training are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- ☆87Updated last year
- Next generation CGRA generator☆118Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆52Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆98Updated 5 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆61Updated 5 months ago
- The Task Parallel System Composer (TaPaSCo)☆114Updated 3 weeks ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated last week
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 2 months ago
- ☆89Updated this week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated this week
- ☆60Updated 2 years ago
- ☆61Updated this week
- ☆17Updated 2 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 2 months ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year