intel / fpga-trainingLinks
☆35Updated last year
Alternatives and similar repositories for fpga-training
Users that are interested in fpga-training are comparing it to the libraries listed below
Sorting:
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Heterogeneous Accelerated Computed Cluster (HACC) Resources Page☆22Updated 3 months ago
- Next generation CGRA generator☆118Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆116Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 6 months ago
- ☆87Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆170Updated last week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated this week
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆40Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- ☆60Updated 2 years ago
- A OpenCL-based FPGA benchmark suite for HPC☆37Updated 11 months ago
- ☆15Updated 4 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 3 years ago
- Rodinia Benchmark Suite for OpenCL-based FPGAs☆31Updated 2 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- The Task Parallel System Composer (TaPaSCo)☆116Updated 2 weeks ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆73Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆14Updated 2 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- Heterogeneous simulator for DECADES Project☆32Updated last year