Xilinx / xaccLinks
Heterogeneous Accelerated Computed Cluster (HACC) Resources Page
☆21Updated 3 weeks ago
Alternatives and similar repositories for xacc
Users that are interested in xacc are comparing it to the libraries listed below
Sorting:
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 10 months ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆41Updated 11 months ago
- ☆36Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆96Updated 2 weeks ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆20Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 3 years ago
- ☆14Updated 2 years ago
- cycle accurate Network-on-Chip Simulator☆28Updated 2 years ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆36Updated 3 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆31Updated 3 months ago
- A polyhedral compiler for hardware accelerators☆59Updated 11 months ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated 7 months ago
- ☆13Updated 3 years ago
- ☆33Updated 10 months ago
- AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…☆24Updated last month
- ☆58Updated last year
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Polyhedral High-Level Synthesis in MLIR☆33Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆41Updated 3 weeks ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A OpenCL-based FPGA benchmark suite for HPC☆34Updated 5 months ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆18Updated 6 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆50Updated 3 months ago
- ☆29Updated 6 years ago