xupsh / ccc2021
view at https://xupsh.github.io/ccc2021/
☆24Updated 2 years ago
Alternatives and similar repositories for ccc2021:
Users that are interested in ccc2021 are comparing it to the libraries listed below
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- ☆63Updated 6 years ago
- An integrated CGRA design framework☆87Updated last week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆70Updated 3 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆70Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Convolutional Neural Network Using High Level Synthesis☆85Updated 4 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 6 months ago
- ☆71Updated 2 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- An Open-Source Tool for CGRA Accelerators☆60Updated 2 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆77Updated 8 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆56Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- ☆86Updated last year
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆42Updated last year
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆165Updated this week
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆91Updated 3 years ago
- ☆104Updated 4 years ago
- ☆70Updated 5 years ago