xupsh / ccc2021
view at https://xupsh.github.io/ccc2021/
☆23Updated 3 years ago
Alternatives and similar repositories for ccc2021:
Users that are interested in ccc2021 are comparing it to the libraries listed below
- ☆63Updated 6 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- An integrated CGRA design framework☆87Updated last month
- ☆71Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆69Updated 6 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 6 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆74Updated 3 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated last month
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆28Updated 6 years ago
- Verilog implementation of Softmax function☆63Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆63Updated 3 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆24Updated 8 months ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆62Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- ☆70Updated 5 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆21Updated 5 months ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- ☆23Updated 4 years ago
- A verilog implementation for Network-on-Chip☆72Updated 7 years ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆42Updated last year
- ☆10Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago