maltanar / fpga-booleanring-bfsLinks
Hybrid BFS on Xilinx Zynq
☆18Updated 10 years ago
Alternatives and similar repositories for fpga-booleanring-bfs
Users that are interested in fpga-booleanring-bfs are comparing it to the libraries listed below
Sorting:
- A Vector Caching Scheme for Streaming FPGA SpMV Accelerators☆10Updated 10 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- Rapid system integration of high-level synthesis kernels using the LEAP FPGA framework☆12Updated 9 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 6 years ago
- A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency…☆21Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆19Updated 6 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆43Updated 8 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆27Updated 2 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆24Updated 5 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated last year
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- ☆16Updated 7 years ago
- CNN accelerator☆27Updated 8 years ago
- A parallel and distributed simulator for thousand-core chips☆26Updated 7 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆43Updated 4 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- ☆88Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- Documentation for the entire CGRAFlow☆19Updated 4 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago