Alternatives and similar repositories for AMD_AECG_Summer_School_Projects:

Users that are interested in AMD_AECG_Summer_School_Projects are comparing it to the libraries listed below

• ChunxuGuo / SummerSchool2022
  ☆61Updated 2 years ago
• qixingzhang / SummerSchool2022-Vitis-AI
  Vitis AI Lab: MNIST classifier
  ☆18Updated 2 years ago
• sazczmh / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆38Updated 5 years ago
• matsuda-slab / YOLO_ZYNQ_MASTER
  Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA
  ☆28Updated 3 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆15Updated 5 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆47Updated 5 years ago
• ZhaoqxCN / PYNQ-CNN-ATTEMPT
  Some attempts to build CNN on PYNQ.
  ☆24Updated 5 years ago
• a2824256 / HLS-LeNet
  The CNN based on the Xilinx Vivado HLS
  ☆37Updated 3 years ago
• gl9544 / vit_transformer_fpga
  ☆14Updated last year
• GeneralZDS / FPGA-DCNN-Accelerator
  基于HLS的高效深度卷积神经网络FPGA实现方法
  ☆69Updated 5 years ago
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆63Updated 3 months ago
• Memory-bread / SSD_IN_PYNQ
  a project build the SSD net in pynq-z2
  ☆15Updated 4 years ago
• peilin-chen / hls_for_cnn_mnist
  【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码
  ☆74Updated 2 years ago
• bird1and1fish / Frame_Difference
  FPGA实现动态图像识别
  ☆20Updated 4 years ago
• YutongChenVictor / Fpga-accelerator-demos
  some interesting demos for starters
  ☆76Updated 2 years ago
• jiangwx / SkrSkr
  The second place winner for DAC-SDC 2020
  ☆97Updated 3 years ago
• xbdxwyh / yolov3_fpga_project
  ☆52Updated 2 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆86Updated 4 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆98Updated 3 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆37Updated 9 months ago
• XueTianyu24 / cnn_accelerator
  【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
  ☆142Updated 2 years ago
• ignperez-udec / MobileNet-V2-inference-HLS
  Codes to implement MobileNet V2 in a FPGA
  ☆25Updated 4 years ago
• yztong / LeNet_RTL
  An LeNet RTL implement onto FPGA
  ☆45Updated 6 years ago
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆17Updated 3 years ago
• Microdent / Handwritten_Mathematical_Calculator_on_FPGA
  A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.
  ☆39Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• 19801201 / Ultra_low_power_CNN_Accelerated
  ☆10Updated 3 years ago
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆63Updated 6 years ago
• AILearnerLi / DAC-SDC-2020-SEUer
  ☆26Updated 2 years ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆51Updated 3 years ago