Maxwellhyh / AMD_AECG_Summer_School_Projects
☆16Updated 2 years ago
Alternatives and similar repositories for AMD_AECG_Summer_School_Projects:
Users that are interested in AMD_AECG_Summer_School_Projects are comparing it to the libraries listed below
- ☆61Updated 2 years ago
- Vitis AI Lab: MNIST classifier☆17Updated 2 years ago
- FPGA实现动态图像识别☆17Updated 4 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆38Updated 4 years ago
- ☆52Updated last year
- a project build the SSD net in pynq-z2☆15Updated 4 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆29Updated 3 years ago
- 可运行☆31Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆90Updated 3 years ago
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- ☆26Updated 2 years ago
- 搭建卷积神经网络并利用FPGA加速实现交通标志识别☆26Updated 4 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆138Updated last year
- some interesting demos for starters☆73Updated 2 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆146Updated last year
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆15Updated 6 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆156Updated 4 months ago
- An LeNet RTL implement onto FPGA☆44Updated 6 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 6 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆15Updated 5 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆41Updated 2 weeks ago
- A DNN Accelerator implemented with RTL.☆63Updated 2 months ago
- 使用FPGA实现CNN模型☆13Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 5 years ago