Maxwellhyh / AMD_AECG_Summer_School_ProjectsLinks
☆16Updated 2 years ago
Alternatives and similar repositories for AMD_AECG_Summer_School_Projects
Users that are interested in AMD_AECG_Summer_School_Projects are comparing it to the libraries listed below
Sorting:
- ☆61Updated 2 years ago
- Vitis AI Lab: MNIST classifier☆18Updated 2 years ago
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆28Updated 3 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆38Updated 5 years ago
- A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.☆40Updated 4 years ago
- The CNN based on the Xilinx Vivado HLS☆36Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 4 months ago
- ☆26Updated 2 years ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- Open-source of MSD framework☆16Updated last year
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- ☆52Updated 2 years ago
- ☆10Updated 3 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆14Updated 10 months ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆38Updated 10 months ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆82Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- ☆29Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆56Updated 4 months ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- ☆15Updated last year
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 4 years ago