Alternatives and similar repositories for ml4dv

Users that are interested in ml4dv are comparing it to the libraries listed below

• shailja-thakur / VGen
  ☆171Updated 9 months ago
• gpt4rtl / AutoSVA2
  ☆16Updated last year
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆121Updated 8 months ago
• AUCOHL / RTL-Repo
  RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
  ☆14Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆85Updated last year
• AutoBench / AutoBench
  ☆24Updated 3 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆24Updated 3 months ago
• shailja-thakur / AutoChip
  ☆30Updated 4 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆25Updated 5 months ago
• magicYang1573 / llm-hardware-test-generation
  ☆31Updated last year
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆210Updated 5 months ago
• IPRC-DIP / CodeV
  ☆44Updated last month
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆35Updated 8 months ago
• HWSec-UNC / Sylvia
  ☆16Updated last month
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated last week
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆288Updated 5 months ago
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆32Updated 6 months ago
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆23Updated 6 years ago
• DfX-NYUAD / LLM4IC
  LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
  ☆27Updated last year
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆17Updated 5 years ago
• masc-ucsc / hdlagent
  LLM Agent for Hardware Description Language
  ☆20Updated last month
• aebeljs / VeRLPy
  VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…
  ☆27Updated 2 years ago
• efeslab / hardware-bugbase
  ☆18Updated last year
• ucb-bar / midas-release
  MIDAS Public Release
  ☆9Updated 6 years ago
• CommonEvaluationPlatform / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…
  ☆23Updated 9 months ago
• sterin / super-prove-build
  ☆13Updated 4 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆19Updated 8 months ago
• stable-lab / MAGE
  MAGE: A Multi-Agent Engine for Automated RTL Code Generation
  ☆52Updated 3 months ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago