Daikon-Sun / Routing-Visualization
Routing Visualization for Physical Design
☆18Updated 6 years ago
Alternatives and similar repositories for Routing-Visualization:
Users that are interested in Routing-Visualization are comparing it to the libraries listed below
- VLSI EDA Global Router☆71Updated 7 years ago
- A LEF/DEF Utility.☆27Updated 5 years ago
- DATC RDF☆49Updated 4 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆48Updated 6 months ago
- Open Source Detailed Placement engine☆35Updated 5 years ago
- Collection of digital hardware modules & projects (benchmarks)☆37Updated 2 months ago
- ☆26Updated 4 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆53Updated 4 years ago
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆39Updated 6 years ago
- Global Router Built for ICCAD Contest 2019☆30Updated 4 years ago
- GPU-based logic synthesis tool☆79Updated 6 months ago
- ☆23Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆122Updated 6 months ago
- UCSD Detailed Router☆82Updated 4 years ago
- Power grid analysis☆19Updated 4 years ago
- A parallel global router using the Galois framework☆27Updated last year
- Optimal gate sizing of digital circuits using geometric programming☆10Updated 8 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆26Updated 2 years ago
- EDA physical synthesis optimization kit☆50Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆126Updated last year
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆109Updated last month
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆20Updated 6 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆41Updated 4 years ago
- ☆29Updated last year
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆16Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 4 years ago