Daikon-Sun / Routing-Visualization
Routing Visualization for Physical Design
☆19Updated 6 years ago
Alternatives and similar repositories for Routing-Visualization:
Users that are interested in Routing-Visualization are comparing it to the libraries listed below
- VLSI EDA Global Router☆72Updated 7 years ago
- DATC RDF☆49Updated 4 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- A LEF/DEF Utility.☆28Updated 5 years ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆51Updated 9 months ago
- Global Router Built for ICCAD Contest 2019☆31Updated 5 years ago
- ☆25Updated 2 years ago
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆39Updated 6 years ago
- An analytical VLSI placer☆28Updated 3 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- EDA physical synthesis optimization kit☆52Updated last year
- A parallel global router using the Galois framework☆27Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆130Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆54Updated 5 months ago
- UCSD Detailed Router☆85Updated 4 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆125Updated 9 months ago
- Power grid analysis☆19Updated 4 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆25Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆27Updated 3 years ago
- Optimal gate sizing of digital circuits using geometric programming☆9Updated 8 years ago
- ☆29Updated 4 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆55Updated 2 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 6 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆45Updated 3 months ago