Alternatives and similar repositories for skywater-pdk-libs-sky130_fd_sc_hd:

Users that are interested in skywater-pdk-libs-sky130_fd_sc_hd are comparing it to the libraries listed below

• google / skywater-pdk-actions
  GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk
  ☆12Updated 3 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_bd_sram
  SRAM build space for the GF180MCU provided by GlobalFoundries.
  ☆10Updated 2 years ago
• google / skywater-pdk-libs-sky130_fd_pr
  Primitives for SKY130 provided by SkyWater.
  ☆23Updated 10 months ago
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
  9 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆16Updated 2 years ago
• google / globalfoundries-pdks
  Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
  ☆47Updated 2 years ago
• google / skywater-pdk-libs-sky130_fd_io
  IO and periphery cells for SKY130 provided by SkyWater.
  ☆9Updated last year
• efabless / caravel-lite
  ☆15Updated 2 months ago
• google / skywater-pdk-libs-sky130_fd_bd_sram
  SRAM build space for SKY130 provided by SkyWater.
  ☆22Updated 3 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_io
  IO and periphery cells for the GF180MCU provided by GlobalFoundries.
  ☆13Updated 2 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆12Updated 4 years ago
• efabless / mpw_precheck
  ☆36Updated 3 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• google / globalfoundries-pdk-ip-gf180mcu_fd_ip_sram
  SRAM macros created for the GF180MCU provided by GlobalFoundries.
  ☆17Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 6 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• google / skywater-pdk-libs-sky130_fd_pr_reram
  SKY130 ReRAM and examples (SkyWater Provided)
  ☆36Updated 2 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last month
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• google / skywater-pdk-libs-sky130_bag3_pr
  BAG (BAG AMS Generator) Primitives Library for SKY130
  ☆16Updated last year
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
  7 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆23Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 5 months ago
• lowRISC / lowrisc-toolchains
  UNSUPPORTED INTERNAL toolchain builds
  ☆32Updated 3 months ago
• google / verilogpp
  ☆17Updated 7 months ago
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆31Updated 2 months ago
• chipsalliance / AIB-specification
  Home of the Advanced Interface Bus (AIB) specification.
  ☆49Updated 2 years ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆45Updated 4 months ago