f4pga / ideasLinks
Random ideas and interesting ideas for things we hope to eventually do.
☆87Updated 3 years ago
Alternatives and similar repositories for ideas
Users that are interested in ideas are comparing it to the libraries listed below
Sorting:
- FPGA tool performance profiling☆102Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Useful utilities for BAR projects☆31Updated last year
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- FuseSoC standard core library☆139Updated last week
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 5 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ☆56Updated 2 years ago
- ☆113Updated 4 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆135Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- Mutation Cover with Yosys (MCY)☆83Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated 3 weeks ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆138Updated 8 months ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆34Updated 3 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆113Updated 8 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Open-source FPGA research and prototyping framework.☆206Updated 9 months ago
- Bitstream relocation and manipulation tool.☆46Updated 2 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Main page☆126Updated 5 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- Chisel/Firrtl execution engine☆153Updated 9 months ago
- Naive Educational RISC V processor☆83Updated this week