Alternatives and similar repositories for mips-proj5:

Users that are interested in mips-proj5 are comparing it to the libraries listed below

• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 9 months ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• jaypiper / simulator
  ☆27Updated this week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆48Updated 5 months ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• thu-cs-lab / Digital-Design-Docs
  Documentation for Digital Design course
  ☆19Updated last month
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆17Updated last month
• MaxXSoft / Bossa
  BOOM's Simulation Accelerator.
  ☆13Updated 3 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆19Updated 3 weeks ago
• RISMicroDevices / RMM4NC30F2X
  Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022
  ☆10Updated 2 years ago
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• OSCPU / chisel-playground
  ☆64Updated 2 months ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆78Updated last year
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 10 months ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆113Updated 4 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 6 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆34Updated 3 years ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated 9 months ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆39Updated 7 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆38Updated 8 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆30Updated last year
• plctlab / plct-toolbox
  PLCT工具箱
  ☆31Updated 2 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆27Updated 5 years ago