WuSiYu / mips-proj5Links
5级流水线MIPS-lite微系统(北工大计组课设)
☆10Updated 4 years ago
Alternatives and similar repositories for mips-proj5
Users that are interested in mips-proj5 are comparing it to the libraries listed below
Sorting:
- CQU Dual Issue Machine☆38Updated last year
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- nscscc2018☆27Updated 7 years ago
- Naïve MIPS32 SoC implementation☆117Updated 5 years ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆50Updated 2 months ago
- A softcore microprocessor of MIPS32 architecture.☆40Updated last year
- An out-of-order execution algorithm for pipeline CPU, implemented by verilog☆42Updated 7 years ago
- ☆63Updated last month
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated this week
- Uranus MIPS processor by MaxXing & USTB NSCSCC team☆38Updated 5 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- The 'missing header' for Chisel☆21Updated 8 months ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated last year
- 重庆大学硬件综合设计课程实验文档☆39Updated 4 months ago
- PLCT工具箱☆30Updated 3 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆37Updated 3 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆32Updated last year
- Hardware design with Chisel☆35Updated 2 years ago