The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRSTLinks
OpenROAD users should look at this repository first for instructions on getting started
☆101Updated 4 years ago
Alternatives and similar repositories for OPENROAD_USERS_READ_ME_FIRST
Users that are interested in OPENROAD_USERS_READ_ME_FIRST are comparing it to the libraries listed below
Sorting:
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆164Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆163Updated 2 months ago
- Fabric generator and CAD tools.☆215Updated this week
- A complete open-source design-for-testing (DFT) Solution☆178Updated 5 months ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆280Updated last month
- Introductory course into static timing analysis (STA).☆99Updated 6 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆200Updated 5 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆309Updated 3 months ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆200Updated 3 weeks ago
- ☆187Updated 4 years ago
- Logic synthesis and ABC based optimization☆52Updated 2 weeks ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆389Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆200Updated last week
- Fully Open Source FASOC generators built on top of open-source EDA tools☆308Updated 3 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆186Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆118Updated 5 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆47Updated 5 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆74Updated 3 years ago
- ☆174Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- ☆232Updated 10 months ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆223Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆245Updated 4 months ago
- Control and status register code generator toolchain☆167Updated last month
- SystemVerilog synthesis tool☆226Updated 10 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆137Updated 2 weeks ago
- ☆86Updated 3 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆104Updated last year