The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRSTLinks
OpenROAD users should look at this repository first for instructions on getting started
☆101Updated 4 years ago
Alternatives and similar repositories for OPENROAD_USERS_READ_ME_FIRST
Users that are interested in OPENROAD_USERS_READ_ME_FIRST are comparing it to the libraries listed below
Sorting:
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆160Updated 2 years ago
- Introductory course into static timing analysis (STA).☆95Updated 2 months ago
- Logic synthesis and ABC based optimization☆49Updated 2 weeks ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆178Updated 5 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆102Updated 4 years ago
- Fabric generator and CAD tools.☆187Updated last week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆63Updated 2 years ago
- ☆78Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆150Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 7 months ago
- ☆160Updated 2 years ago
- A complete open-source design-for-testing (DFT) Solution☆159Updated 3 weeks ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 4 months ago
- ☆169Updated 3 months ago
- ideas and eda software for vlsi design☆50Updated last week
- Control and status register code generator toolchain☆138Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆136Updated this week
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆122Updated 3 weeks ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆282Updated last month
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆184Updated last month
- ☆111Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆62Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆113Updated this week
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆136Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆219Updated last week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago