ansonn / esl_systemc
systemc建模相关
☆27Updated 10 years ago
Alternatives and similar repositories for esl_systemc:
Users that are interested in esl_systemc are comparing it to the libraries listed below
- ☆27Updated 4 years ago
- A repository for SystemC Learning examples☆67Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆43Updated 6 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- ☆16Updated 6 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- A MCU implementation based PODES-M0O☆18Updated 5 years ago
- ☆36Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Archives of SystemC from The Ground Up Book Exercises☆30Updated 2 years ago
- Contains commonly used UVM components (agents, environments and tests).☆28Updated 6 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆38Updated last year
- PCI Express controller model☆55Updated 2 years ago
- Implementation of the PCIe physical layer☆37Updated 3 months ago
- eyeriss-chisel3☆40Updated 2 years ago
- SystemC training aimed at TLM.☆28Updated 4 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆54Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Updated 5 years ago
- IOPMP IP☆14Updated 6 months ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 weeks ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- ☆9Updated 4 years ago
- ☆21Updated 5 years ago